SEU emulation in industrial SoCs combining microprocessor and FPGA

Vurgaftman, I.; Bidarte, Unai; Gomez-Cornejo, Julen; Jiménez, Jaime; Lázaro, Jesús

doi:10.1016/j.ress.2017.09.028

Cited by 17 publications

(11 citation statements)

References 33 publications

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“…Methods like Villalta et al (2018) propose to emulate a component failure and observe the reaction of the platform. Nevertheless, the quality of the results highly depends on the capacity to ensure the completeness of such approach.…”

Section: Failure Modes Identificationmentioning

confidence: 99%

Multi-Core Processor: Stepping Inside the Box

Cuenot¹,

Delmas²,

Pagetti³

2021

Proceedings of the 31st European Safety and Reliability Conference (ESREL 2021)

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The last decade has seen the emergence of multi-core and many-core processors replacing historical uni-processors in most of the applicative domains. There is no doubt that the next generation of aircraft will rely on these technologies raising major issues especially with regard to safety assessment. Indeed, currently, a processor is considered as a black-box component where any single internal failure leads to the loss of all executed software. Due to the numerous resources provided by such platform, position papers like the CAST-32A promote a finer analysis of the safety impact of internal component failures. Hence there is a necessity to open the box and see such a processor as a sub-system. We introduce a formal modeling framework capturing the main characteristics of software/hardware failure propagation. This framework is applied on a simplified UAV control use-case.

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Section: Failure Modes Identificationmentioning

confidence: 99%

Multi-Core Processor: Stepping Inside the Box

Cuenot¹,

Delmas²,

Pagetti³

2021

Proceedings of the 31st European Safety and Reliability Conference (ESREL 2021)

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“…where 𝜇 𝑘 = 𝜌 𝑘 • 𝑇𝑆 𝜏 • 𝐶𝑇 𝜏 (6) in which 𝜌 𝑘 is the 𝑘-bit event environmental SER expressed per bit per time unit. Thus, the rate of the 𝑘-bit event of the task (𝜇 𝑘 ) increases with task size and task computation time [28]. For practical reasons, we will accept that the occurrence of 𝑘-bit events is negligible for 𝑘 > 𝑀.…”

Section: Reliability Model and Its Validationmentioning

confidence: 99%

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Ramezani

Clemente

Franco

2020

Reliability Engineering & System Safety

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“…However, the high cost of these tests make them unaffordable for many institutions. Lower-cost solutions have been presented, which are based on fault emulation [14], to generate affordable verification mechanisms. In this work, the proposed fault mitigation strategies have been evaluated using a fast injection procedure, implemented with the SEM-IP and commanded by the R5 cores.…”

Section: State Of the Artmentioning

confidence: 99%

“…When using the monitor interface, error injection latency tested on UltraScale+ VU3P at ICAP maximum frequency and assuming no throttling on the Monitor Interface is 81μs [9]. Our implemented command interface version significantly improves fault injection rate of recent works, from 26 to ~60000 per second [14]. However, with this method, faults cannot be injected on every bit of the configuration memory as explained below.…”

Section: A Fault Injection Through Sem-ipmentioning

confidence: 99%

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics

Pérez

Otero

Torre

2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Zynq UltraScale+ (ZU+) devices contain a variety of computing fabrics of different nature and purpose to support complex adaptive heterogeneous system applications with active fault tolerance techniques. Namely, the Processor Management Unit (PMU) and the R5 processors are candidates for hosting the scrubbing and reconfiguration tasks, as well as for dealing with other fault detection and repair tasks originated in, for instance, Triple-Modular Redundancy (TMR) structures in the reconfigurable logic section. This paper contains a performance and trade-off analysis of different scrubbing techniques (ECCbased and readback) when handled by different components such as the Soft-Error Mitigation IP (SEM-IP), the Real Time Processing Unit (RPU) processors or the Platform Management Unit (PMU) processor. The implementation of the measured strategies has been selected in order to be compatible with dynamic and partial reconfiguration functions in order to also have higher additivity at HW level.

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SEU emulation in industrial SoCs combining microprocessor and FPGA

Cited by 17 publications

References 33 publications

Multi-Core Processor: Stepping Inside the Box

Multi-Core Processor: Stepping Inside the Box

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics

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