SEU Hardened Flip-Flop Based on Dynamic Logic

Xuan, SheXiao; Li, N.; Tong, Jiarong

doi:10.1109/tns.2013.2281138

Cited by 26 publications

(16 citation statements)

References 27 publications

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“…It is likely to cause voltage transients at the nodes [8,9,10,11,12,13]. If the voltage transients occur at the storage nodes of latches, the data stored might be flipped [7,14,15,16,17,18].…”

Section: Introductionmentioning

confidence: 99%

A single event upset tolerant latch with parallel nodes

Liu

Lin

et al. 2019

IEICE Electron. Express

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A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dualmodular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.

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Section: Introductionmentioning

confidence: 99%

A single event upset tolerant latch with parallel nodes

Liu

Lin

et al. 2019

IEICE Electron. Express

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“…A traditional latch or flip-flop is susceptible to particle strikes. During the hold time, an SEU may upset the logic state of the latch or flip-flop, and the faulty values are not corrected until a new value is written in the latch or flip-flop [21].…”

Section: Introductionmentioning

confidence: 99%

“…The main drawback of TMR is excessive area overhead. TMR has more than 200% area overhead than the original circuit after taking into account the majority voter [21]. Error correction codes (ECCs) are another popular technique for protecting memory against SEUs.…”

Section: Introductionmentioning

confidence: 99%

“…A latch can be hardened to protect against SEU. An SEU hardened latch is designed by adding additional transistors to its basic circuit structure such that the capacitance of sensitive nodes or the strength of sensitive transistors is increased [21]. An SEU hardened flip-flop can be constructed with such hardened latches.…”

Section: Introductionmentioning

confidence: 99%

“…A firebird flip-flop uses four parallel redundant latches and C-elements to eliminate SEUs [20]. An SEU hardened flip-flop mitigates SEU via a dynamic logic based error detection circuit and a multiplexer [21]. A radiation hardened flip-flop avoids SEU by separating critical components and utilizing cross-coupled dual-modular redundancy [22].…”

Section: Introductionmentioning

confidence: 99%

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SEU Hardened Placement and Routing Based on Slack Reduction

Xuan

Li²

2014

IEEE Trans. Nucl. Sci.

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This paper presents an SEU hardened placement and routing scheme targeted at an application specific integrated circuit. The proposed scheme reduces the positive slack so that the incorrect value caused by SEU in a flip-flop is less likely to be captured by a subsequent flip-flop. Experimental results demonstrate that the proposed scheme can not only reduce the SEU susceptibility of traditional non-hardened circuits but also improve the SEU resistance of hardened circuits further.Index Terms-Hardened by design, placement and routing, radiation effects, single event upset (SEU).

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A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module

Adapur

Kumar

2018

Soft Computing Systems

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SEU Hardened Flip-Flop Based on Dynamic Logic

Cited by 26 publications

References 27 publications

A single event upset tolerant latch with parallel nodes

A single event upset tolerant latch with parallel nodes

SEU Hardened Placement and Routing Based on Slack Reduction

A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module

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