SEU-induced persistent error propagation in FPGAs

Morgan, Keith S.; Caffrey, Michael; Graham, Paul; Johnson, Eric K.; Pratt, B.; Wirthlin, Michael

doi:10.1109/tns.2005.860674

Cited by 84 publications

(44 citation statements)

References 8 publications

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“…One example is Partial TMR as discussed by Pratt et al in [Pratt et al 2006;. The basic idea is to apply TMR only to feedback paths and optionally to their inputs to avoid so-called persistent errors [Morgan et al 2005] in state-dependent logic. By doing so, only failures with a transient nature can occur.…”

Section: User Logicmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Section: User Logicmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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“…Markov model theory and experimental validation for such systems is presented in [44], where reliability is shown to improve with increasing number of partitions. Another consideration is the possibility of having persistent errors [46]. Such type of errors cannot be mitigated by scrubbing, and the system becomes permanently unavailable.…”

Section: A Reliability and Availabilitymentioning

confidence: 99%

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Herrera-Alzu

López‐Vallejo

2013

IEEE Trans. Nucl. Sci.

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Abstract-SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

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“…Graham et al [13] Wirthlin et al [16], [26], [39] have developed a fault injection tool that identifies the sensitive configuration bits of the device for any given FPGA design. This tool operates by artificially injecting faults within the configuration bitstream and monitoring the behavior of the device.…”

Section: Previous Workmentioning

confidence: 99%

“…By testing every configuration bit of the device, a detailed sensitivity profile of a given design can be created. This fault injection tool has been used to characterize the sensitivity of many FPGA designs [16], [26].…”

Section: Previous Workmentioning

confidence: 99%

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Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Asadi¹,

Tahoori

Mullins³

et al. 2007

IEEE Trans. Nucl. Sci.

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Abstract-Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, single event upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.In this paper we analyze the soft error vulnerability of FPGAs used in information systems. Since the reliability requirements of these high performance information subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in overall system reliability. We present an analytical approach (versus fault injection) for soft error rate estimation in FPGA-based designs. We also validate the projections produced by our analytical model using field error rates obtained from failure data obtained from a large FPGA-based design used in the Logical Unit Module board of a commercial information system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied).Index Terms-Error analysis, field programmable gate arrays (FPGA), information systems, logic circuit fault tolerance, reliability estimation, reliability modeling, SRAM chips (SRAM-based FPGAs).

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SEU-induced persistent error propagation in FPGAs

Cited by 84 publications

References 8 publications

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

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