Shadow And-Inverter Cones

Parandeh-Afshar, Hadi; Zgheib, Grace; Novo, David; Purnaprajna, Madhura; Ienne, Paolo

doi:10.1109/fpl.2013.6645566

Cited by 4 publications

(4 citation statements)

References 6 publications

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“…Then an enhanced AIC architecture was proposed as a shadow logic, placed behind LUTs [12]. Irrespective of its architectural placement, this enhanced design adds to the initial AIC architecture programmable inversions at the inputs of the first level nodes, as shown in Figure 6.…”

Section: Aic Logic Elementmentioning

confidence: 99%

“…We use the AIC technology mapper described in Parandeh-Afshar et al [10] and include a final area recovery pass [12]. The mapping includes basically three phases.…”

Section: Aic Technology Mappermentioning

confidence: 99%

“…Perhaps more importantly, the modeling of the new logic cluster was somewhat rough and no real global routing results were presented, the overall routing contribution being estimated through statistical parameters extrapolated from LUT-only experiments. Some aspects of the architecture have been refined in successive papers without really addressing the fundamental modeling questions [12,11]. We think that a more comprehensive analysis of AICs is worth it, before they can be considered as serious alternative to LUTs.…”

Section: Introductionmentioning

confidence: 99%

“…The enhanced AIC architecture with programmable inversion at the inputs of the first level nodes, reproduced from the paper which introduced the improvement[12].…”

mentioning

confidence: 99%

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Revisiting and-inverter cones

Zgheib

Yang

Huang

et al. 2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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And-Invert Cones (AICs) have been suggested as an alternative to the ubiquitous Look-Up Tables (LUTs) used in commercial FPGAs. The original article suggesting the new architecture made some untested assumptions on the circuitry needed to implement AIC architectures and did not develop completely the toolset necessary to assess comprehensively the idea. In this paper, we pick up the architecture that some of us proposed in the original AIC paper and try to implement it as thoroughly as we can afford. We build all components for the logic cluster at transistor level in a 40 nm technology as well as a LUT-based architecture inspired by Altera's Stratix IV. We first determine that the characteristics of our LUT-based architecture are reasonably similar to those of the commercial counterpart. Then, we compare the AIC architecture to the baseline on a number of benchmarks, and we find a few difficulties that had been overlooked before. We thus explore other design possibilities around the original design point and show their detailed impact. Finally, we discuss how the very structure of current logic clusters seems not perfectly appropriate for getting the best out of AICs and conclude that, even though they are not confirmed as an immediate blessing today, AICs still offer rich research opportunities.

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Section: Aic Logic Elementmentioning

confidence: 99%

“…We use the AIC technology mapper described in Parandeh-Afshar et al [10] and include a final area recovery pass [12]. The mapping includes basically three phases.…”

Section: Aic Technology Mappermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The enhanced AIC architecture with programmable inversion at the inputs of the first level nodes, reproduced from the paper which introduced the improvement[12].…”

mentioning

confidence: 99%

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