SHAKTI-MS: a RISC-V processor for memory safety in C

Das, Sourav; Unnithan, R. Harikrishnan; Menon, Arun; Rebeiro, Chester; Kamakoti, V.

doi:10.1145/3316482.3326356

Cited by 15 publications

(9 citation statements)

References 31 publications

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“…Menon et al [51] developed a RISC-V 64 bit processor Shakti-T, which supports a customized ISA extension containing 8 new instructions for temporal and spatial memory attack protection. Das et al [62] developed another RISC-V processor Shakti-MS. They proposed two new instructions and simply modified the compiler, which can automatically insert these new instructions to realize memory protection during hardware operation.…”

Section: H Securitymentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: H Securitymentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…As shown in Table 1, some approaches mixed the way to compensate for limitations. For example, ALEXIA and Shakti-MS mixed the per-object and per-pointer methods for the bounds check of the sub-object [8,16]. Further details are provided in later sections.…”

Section: Related Workmentioning

confidence: 99%

L4 Pointer: An efficient pointer extension for spatial memory safety support without hardware extension

Mok¹,

Cho²

2023

Preprint

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Since buffer overflow has long been a frequently occurring, high-risk vulnerability, various methods have been developed to support spatial memory safety and prevent buffer overflow. However, every proposed method, although effective in part, has its limitations. Due to expensive boundchecking or large memory intaking for metadata, the softwareonly support for spatial memory safety inherently entails runtime overhead. Contrastingly, hardware-assisted methods are not available without specific hardware assistants. To mitigate such limitations, Herein we propose L4 Pointer, which is a 128-bit pointer extended from normal 64-bit virtual addresses. By using the extra bits and widespread SIMD operations, L4 Pointer shows less slow-down and higher performance without hardware extension than existing methods.

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“…Hardware-based checking. Many solutions utilize dedicated hardware support to perform memory checks [32], [33], [35], [79], [122], [125]. Watchdog [35] follows the behavior similar to CETS.…”

Section: Pointer Dereferences Checkingmentioning

confidence: 99%

Automated Use-After-Free Detection and Exploit Mitigation: How Far Have We Gone?

Gui

Song

Xiong

et al. 2022

IIEEE Trans. Software Eng.

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C/C++ programs frequently encounter memory errors, such as Use-After-Free (UAF), buffer overflow, and integer overflow. Among these memory errors, UAF vulnerabilities are increasingly being exploited by attackers to disrupt critical software systems, leading to serious consequences, such as remote code execution and data breaches. Researchers have proposed dozens of approaches to detect UAFs in testing environments and to mitigate UAF exploit in production environments. However, to the best of our knowledge, no comprehensive studies have evaluated and compared these approaches. In this paper, we shed light on the current UAF detection and exploit mitigation approaches and provide a systematic overview, comprehensive comparison, and evaluation. Specifically, we evaluate the effectiveness and efficiency of publicly available UAF detection and exploit mitigation tools. The experimental results show that static UAF detectors are suitable for detecting intra-procedural UAFs but are not sufficient to detect inter-procedural UAFs in real-world programs. Dynamic UAF detectors are still the first choice for detecting inter-procedural UAFs. Our evaluation also demonstrates that the runtime overhead of existing UAF exploit mitigation tools is relatively stable whereas the memory overhead may vary dramatically with respect to different programs. Finally, we envision potential valuable future research directions.

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SHAKTI-MS: a RISC-V processor for memory safety in C

Cited by 15 publications

References 31 publications

RISC-V Instruction Set Architecture Extensions: A Survey

RISC-V Instruction Set Architecture Extensions: A Survey

L4 Pointer: An efficient pointer extension for spatial memory safety support without hardware extension

Automated Use-After-Free Detection and Exploit Mitigation: How Far Have We Gone?

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