Shallow Trench Isolation Chemical Mechanical Planarization: A Review

Abstract

Electrical isolation of the billion or so active components in each integrated device is achieved using shallow trench isolation (STI) which requires chemical mechanical planarization (CMP) involving silicon dioxide removal at a high rate and stopping on an underlying silicon nitride film. Several colloidal slurries with various additives can yield the desired high rate selectivity between the oxide and nitride films during CMP while maintaining an acceptably low nitride rate. Here, many of such high selectivity STI CMP slurries described in the literature are reviewed along with the characteristics of the colloidal dispersions like the abrasives, additives, the interactions between them and with the films being planarized and the associated pH range in which the high selectivity is observed. The mechanisms proposed to explain the high reactivity of ceria with oxide, the role of additives in suppressing the nitride removal rate and resulting high selectivity are discussed. Reduction of a multitude of defects in post-CMP processed STI structures still remains an important challenge, especially as the feature sizes continue to shrink. Chemical mechanical planarization (CMP) is one of the important enabling processes in facilitating multilevel metallization (in some cases reaching up to 14 levels) and incorporation of novel gate and channel materials at the component level in modern semiconductor device manufacturing where its use has become widespread and ubiquitous.1-6 Here, we review recent advances and remaining challenges in one specific application of CMP, the shallow trench isolation (STI) process. STI is a method of electrically isolating active areas using trenches created in the Si substrate around the active elements and filling it with an insulating dielectric, such as silicon dioxide or silicon oxy-nitride or silicon carbonitride.7-11 Process details of the STI structures are available in numerous publications. There are a multitude of techniques available for oxide deposition and even though the resulting oxides have very different properties, for simplicity we do not distinguish between them in this review. For completeness and ease of reference, a schematic representation of the STI process is given in Figure 1. While the trenches are being filled, silicon dioxide also deposits over unwanted areas on the entire wafer (since selective deposition in trenches only is not possible) creating an uneven topography. The excess and unwanted oxide has to be completely removed and CMP has proven to be the only viable and robust global and local planarization capable process technology.Here, as shown in Figure 1, presence of a very thin silicon nitride stop layer (deposited on another thin pad oxide layer to control film stress) is an essential and integral part of the process. This nitride stop layer prevents any damage during planarization to the all-important epitaxially grown surface underneath and is itself removed by a wet etch process subsequent to the overburden oxide removal. Since the integrity of the...

Chemical Mechanical Planarization-Related to Contaminants: Their Sources and Characteristics

“…Residual ceria abrasives are discovered after STI CMP process (Figure 2c) [21,33]. In contrast with a silica abrasive, ceria abrasive is more strongly coupled with the dielectric materials (in particular, SiO 2 film) via the formation of strong Ce-O-Si bonding [4,34]. It is well known that the surface Ce 3+ species are the active sites for the formation of strong Ce-O-Si bonds with SiO 2 films during polishing [4,21].…”

“…Moreover, silica abrasives are weakly bound to the films and can be easy to be removed by under-cut and particle lift-off or their combination during cleaning [15]. Ceria-based slurry has been widely used for STI CMP to uniformly polish the step height of SiO 2 , formed by the gap-filling process, and stop on an underlying Si 3 N 4 film [4][5][6]. Residual ceria abrasives are discovered after STI CMP process (Figure 2c) [21,33].…”

“…One of the important FEOL CMP processes is the shallow trench isolation (STI) CMP. STI CMP uniformly polishes the step height of SiO 2 , formed by the gap-filling process, and stops on an underlying Si 3 N 4 film [4][5][6]. MOL CMP processes include the necessary steps to connect the individual transistors by mainly polishing W contact metal/liner and interlayer dielectric (ILD) layer [7,8].…”

Role of Ce3+Ions in Achieving High Silicon Nitride Polish Rates

“…4,24,25 However, if the positively charged Ce 3+ ions present in solution can bind to the negatively charged oxide surface, they can block a large fraction of the active sites on the wafer surface, as shown in Figure 14b.…”

A review on chemical and mechanical phenomena at the wafer interface during chemical mechanical planarization

“…The FEOL process contains all the necessary steps to build the device architecture with a variety of CMP steps for different layer combinations of SiO 2 , Si 3 N 4 , and poly-Si stop layers, SiC, SiCN, etc. and the high-k/metal gate structures [3,4]. The MOL processes are introduced to connect the individual cambridge.org/JMR 1 transistors.…”