Shaping gate channels for improved devices

Gupta, Puneet; Kahng, Andrew B.; Kim, Young‐Min; Shah, Sagar; Sylvester, Dennis

doi:10.1117/12.772889

Cited by 7 publications

(1 citation statement)

References 12 publications

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“…From an existing transistor, we create a leakage-optimized device with less leakage and the same (or similar) delay as the original rectangular transistor. Due to the unequal distribution of on and off current densities across the width of a channel, different channel lengths across the device width show different V th , and thus the leakage current varies across the channel width [4,5]. The "edge effect" indicates that the channel lengths at both device edges are responsible for greater variations in the drive current and leakage current than at the center [5].…”

Section: Introductionmentioning

confidence: 97%

Transistor layout optimization for leakage saving

Ryu

Kang

Kim

2013

2013 International SoC Design Conference (ISOCC)

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In this paper, we investigate electrical effects of transistor layout shape (both in the channel and diffusion) on the performance and leakage current. Through layout optimization techniques, we propose a novel intra-gate biasing technique to reduce leakage current while maintaining drive current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. Diffusion rounding is another interesting effect which happens due to the imperfect source and drain profile in the sub-wavelength lithography regime. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased I on with decreased I off because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement both in the on-current (driving) and the off-current (leakage).

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Section: Introductionmentioning

confidence: 97%