SHARC - Simulation and Verification of Hierarchical Embedded Microelectronic Systems

Weissnegger, Ralph; Kreiner, Christian; Pistauer, Markus; Römer, Kay Uwe; Steger, Christian

doi:10.1016/j.procs.2017.05.407

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Cited by 5 publications

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“…The increasing complexity of software systems will raise the cost of production [4] and reliable V&V approaches are crucial as a single bug that goes unnoticed can be extremely costly for a company [9]. Even without AI being involved, currently, around 60% of vehicle recalls are due to software bugs [10].…”

Section: Figure 1 Sae Levelsmentioning

confidence: 99%

Software Verification and Validation of Safe Autonomous Cars: A Systematic Literature Review

et al. 2021

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Section: Figure 1 Sae Levelsmentioning

confidence: 99%

Software Verification and Validation of Safe Autonomous Cars: A Systematic Literature Review

et al. 2021

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Simulation-based Holistic Functional Safety Assessment for Networked Cyber-Physical Systems

Fraccaroli

Quaglia

Fummi

2018

2018 Forum on Specification &Amp; Design Languages (FDL)

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SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment

Chen

2021

J CIRCUIT SYST COMP

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We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach.

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SHARC - Simulation and Verification of Hierarchical Embedded Microelectronic Systems

Cited by 5 publications

References 11 publications

Software Verification and Validation of Safe Autonomous Cars: A Systematic Literature Review

Software Verification and Validation of Safe Autonomous Cars: A Systematic Literature Review

Simulation-based Holistic Functional Safety Assessment for Networked Cyber-Physical Systems

SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment

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