Shared Memory Consistency Models: A Tutorial

Adve, Sarita V.; Gharachorloo, Kourosh

doi:10.21236/ada638015

Cited by 185 publications

(295 citation statements)

References 4 publications

Supporting

Mentioning

295

Contrasting

Order By: Relevance

“…Memory consistency models [1,2] constrain memory behaviors with respect to read and write operations from multiple processors, providing formal specifications of how the memory system will appear to the programmer. Each of these models offers a tradeoff between programming simplicity and high performance.…”

Section: Sequential Consistencymentioning

confidence: 99%

“…(Discussion) For performance reasons, different architectures that use relaxed memory models provide various types of fence instructions that enforce different memory orders [2,12]. For example, in Intel IA-32, there exists three types of fence instructions, i.e., mfence, lfence and sfence.…”

Section: Actual Hardwarementioning

confidence: 99%

“…When a C-Fence instruction is issued, its fence-id and associate-id are stored in the active table (1). Upon a processor is about to issue a C-Fence, it sends a request to consult the active table using the fence-id (2). The active table processes the request by checking associate-ids in the table, and then responds to the processor whether the C-Fence can be issued (3).…”

Section: Distributed Activementioning

confidence: 99%

“…1, which is taken from an implementation of the Dekker's algorithm [2,10]. This algorithm is designed to allow only one processor to enter the critical section at a time, using two shared memory variables flag1 and flag2.…”

Section: Introductionmentioning

confidence: 99%

“…For example, write buffering cannot be directly utilized, if SC needs to be guaranteed. Therefore, for performance reasons, researchers have proposed relaxed memory consistency models [2,3] at the cost of programming complexity. However, in recent work researchers have shown that it might be possible for architectures to support SC at a high performance using sophisticated speculative techniques [13][14][15]30].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Efficient Sequential Consistency Using Conditional Fences

Lin

Nagarajan

Gupta

2011

Int J Parallel Prog

View full text Add to dashboard Cite

Among the various memory consistency models, the sequential consistency (SC) model is the most intuitive and enables programmers to reason about their parallel programs the best. Nevertheless, processor designers often choose to support relaxed memory consistency models because the weaker ordering constraints imposed by such models allow for more instructions to be reordered and enable higher performance. Programs running on machines supporting weaker consistency models can be transformed into ones in which SC is enforced. The compiler does this by computing a minimal set of memory access pairs whose ordering automatically guarantees SC. To ensure that these memory access pairs are not reordered, memory fences are inserted. Unfortunately, insertion of such memory fences can significantly slowdown the program. We observe that the ordering of the minimal set of memory accesses that the compiler strives to enforce, is typically already enforced in the normal course of program execution. A study we conducted on programs with compiler inserted memory fences shows that only 8% of the executed instances of the memory fences are really necessary to ensure SC. Motivated by this study we propose the conditional fence mechanism, known as C-Fence that utilizes compiler information to decide dynamically if there is a need to stall at each fence, only stalling when necessary. Our experiments with SPLASH-2 benchmarks show that, with C-Fences and a centralized 123 Int J Parallel Prog (2012) 40:84-117 85 active table, programs can be transformed to enforce SC incurring only 12% slowdown, as opposed to 43% slowdown using normal fence instructions. Our approach requires very little hardware support (<350 bytes of on-chip-storage) and it avoids the use of speculation and its associated costs. Furthermore, to ameliorate the contention in the centralized active table arising from the increasing number of processors, we also design a distributed active table, which further improves the performance of C-Fence for a larger number of processors.

show abstract

Section: Sequential Consistencymentioning

confidence: 99%

Section: Actual Hardwarementioning

confidence: 99%

Section: Distributed Activementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Efficient Sequential Consistency Using Conditional Fences

Lin

Nagarajan

Gupta

2011

Int J Parallel Prog

View full text Add to dashboard Cite

show abstract

Shared Memory Multiprocessors

Lastovetsky

2003

Parallel Computing on Heterogeneous Networks

View full text Add to dashboard Cite

Shared Memory Multiprocessors

Zhang

Parashar

2007

Wiley Encyclopedia of Computer Science and Engineering

View full text Add to dashboard Cite

Shared memory multiprocessors are multiprocessor systems that logically implement a single global address space. The model for parallel programming based on such systems, the shared address space model, is straightforward and frees programmers from the tedious and sometimes complicated task of orchestrating all communication and snychronization through explicit message passing to access remote data. As a result, this class of multiprocessor systems has received much commercial as well as research interest.

show abstract

Shared Memory Consistency Models: A Tutorial

Cited by 185 publications

References 4 publications

Efficient Sequential Consistency Using Conditional Fences

Efficient Sequential Consistency Using Conditional Fences

Shared Memory Multiprocessors

Shared Memory Multiprocessors

Contact Info

Product

Resources

About