Shielding structures for through silicon via (TSV) to active circuit noise coupling in 3D IC

Abstract

Through silicon via (TSV) has been extensively highlighted as the key solution for small form factor wide bandwidth, and low power consumption with compactly integrating multiple chips. Despite the many advantages of TSV based 3-dimensional integrated circuit (3D IC), there are several challenges to be overcome such as noise coupling, fabrication process limits, and failure issues. In this paper, we proposed shielding structures for TSV to active circuit noise coupling in 3D IC. The proposed structures can capture TSV substrate noise by blocking the noise paths to active circuit, LC-VCO in this study. The noise suppression mechanisms are analyzed by the noise coupling coefficient in frequency-domain obtained by 3D electromagnetic simulation. Various shielding structures are investigated and compared with regard to sensitivity of active circuit, such as phase noise of LC-VCO.

Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications

“…Common methods for integrating three dimensions include wafer-on-wafer (W-o-W), chip-on-chip (C-o-C), and chip-on-wafer (C-o-W) stacking. One common technique for vertical device integration in the semiconductor industry is Cu-Cu-WoW bonding [3]- [10]. Modern hardware [11]- [16] integrated in three dimensions may enhance system performance.…”

S-Parameters Optimization in both Segmented and Unsegmented Insulated TSV upto 40GHz Frequency

“…For instance; limited reliability, thermal cycling, electro migration, silicon depletion at or around the via and also shock and vibration. Noise coupling, fabrication process limits and failure issues have been discussed in [10]. However TSV has several advantages such as reducing the delay, power and area.…”