2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) 2016
DOI: 10.1109/isca.2016.34
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Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors

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Cited by 5 publications
(4 citation statements)
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“…It is possible to further duplicate [55] handlers to get more BTB entries [23]. Recent work has also proposed new hardware support for indirect speculation [69] [63] or to directly address BTB entries [41]. Many JVMs mutate bytecode in-place [22] to replace symbolic references with indexes and offsets.…”
Section: Optimizing Fixed Format Interpretersmentioning
confidence: 99%
“…It is possible to further duplicate [55] handlers to get more BTB entries [23]. Recent work has also proposed new hardware support for indirect speculation [69] [63] or to directly address BTB entries [41]. Many JVMs mutate bytecode in-place [22] to replace symbolic references with indexes and offsets.…”
Section: Optimizing Fixed Format Interpretersmentioning
confidence: 99%
“…Capability-based systems [21,32,48,102] provide object-based memory protection and isolation. Typed architectures [2,16,43,44,88] accelerate dynamic type checks. Whereas this prior work focuses on core design and uses a standard cache hierarchy, we focus on redesigning the memory hierarchy.…”
Section: Background On Memory-safe Languagesmentioning
confidence: 99%
“…To overcome this limitation, we could extend ShortCut to index the BTB with bytecode addresses instead of PCs. A similar approach is used in previous BTB proposals [22,25].…”
Section: Applicability To Interpretersmentioning
confidence: 99%
“…The second proposal by Kim et al [25] reduces the overheads of bytecode dispatching in interpreters by overlaying the bytecode jump table on the BTB. This scheme, however, is not flexible enough to support ICs.…”
Section: Related Workmentioning
confidence: 99%