Short-length FIR filters and their use in fast nonrecursive filtering

Mou, Z.-J.; Duhamel, Pierre

doi:10.1109/78.136539

Cited by 124 publications

(54 citation statements)

References 11 publications

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“…FFAs [22,23] work on the principle of algorithmic strength reduction, i.e. they reduce the number of expensive is used by the FFA stru MAC operations at the cost of increased add operations.…”

Section: B Ffa Based Time-shared Filtersmentioning

confidence: 99%

Low power, flexible FIR filters in the digital frontend of green radios

Michael

Vinod

Moy

et al. 2010

21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications

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Abstract-The growing energy footprint and environmental costs of information and communication technologies has created an awareness of the need for greener communications. However, the task of reducing the energy footprint of wireless infrastructure and terminals is daunting due to the requirements of flexibility and reconfigurability in emerging paradigms like 4G. This paper addresses the flexibility and power consumption challenges of channel filtering, which is one of the most computationally intensive kernels in the radio baseband. Power reduction strategies for programmable time-shared filters have been generally focused on the dynamic power, which has been replaced by leakage power as the dominant mode of power consumption in nanoscale CMOS devices. We investigate the role of parallelism in reducing the nanoscale CMOS power consumption. We also propose a class of programmable timeshared filters that are more area efficient than traditional folded direct form filters, when the level of parallelism is increased.

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Section: B Ffa Based Time-shared Filtersmentioning

confidence: 99%

Low power, flexible FIR filters in the digital frontend of green radios

Michael

Vinod

Moy

et al. 2010

21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications

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show abstract

“…This diagonalization approach involves only real-number operations to process the decimated sequences. However, as A4 increases, the derivation becomes complicated and the resulting architecture is highly irregular (as opposed to the DFT approach) [13]. In the verification part, we will use the multirate FIR structure in Fig.…”

Section: Diagonalization Of the Pseudocirculant Matrixmentioning

confidence: 99%

Algorithm-based low-power DSP system design: methodology and verification

Liu

Zhang

et al. 1995

VLSI Signal Processing, VIII

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-We present a low-power design methodology based on the multirate approach for DSP systems. Since the datar rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature t o either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers a systematic tool t o design low-power DSP systems at the algorithmic/architectural level.The proposed low-power multirate design scheme is verified by the implementation of two FIR VLSI chips with different .architectures: One is the normal pipelined design and the other is the multirate FIR design with downsampling rate equal t o two. Using the CMOS power dissipation model, we can predict that the multirate FIR chip consumes only 29% power of the normal FIR chip given the same throughput rate. The predicted results will be verified by measuring real power consumption of both chips.

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“…There is another approach using number theoretic transform, which has advantages when implemented in fixed point arithmetic [2]. There are also variants of block convolution methods considering many aspects of implementation such as input-output delay and hardware/software realizations [3,6]. For the software implementation of block convolution on modern computers with floating point arithmetics, the traditional OSA is still the most popular method owing to its simple data manipulation and the availability of powerful FFT libraries tailored for the given processor architecture.…”

Section: Introductionmentioning

confidence: 99%

A New Overlap Save Algorithm for Fast Block Convolution and Its Implementation Using FFT

Kuk

Kim

Cho

2010

J Sign Process Syst

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Convolution of data with a long-tap filter is often implemented by overlap save algorithm (OSA) using fast Fourier transform (FFT). But there are some redundant computations in the traditional OSA because the FFT is applied to the overlapped data (concatenation of previous block and the current block) while the DFT computations are recursive. In this paper, we first analyze the redundancy by decomposing the OSA into two processes related to the previous and current block. Then we eliminate the redundant computations by introducing a new transform which is applied only to the current data, not to the overall overlapped data. Hence the size of transform is reduced by half compared to the traditional OSA. The new transform is in the form of DFT and it can be implemented by defining a new butterfly structure. However we implement it by a cascade of twiddle factor and conventional FFT in this paper, in order to use the FFT libraries in PC and DSP. The computational complexity in this case is analyzed and compared with the existing methods. In the experiment, the proposed method is applied to several block convolutions and partitionedblock convolutions. The CPU time is reduced more than expected from the arithmetic analysis, which implies that the reduced transform size gives additional advantage in data manipulation.

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Short-length FIR filters and their use in fast nonrecursive filtering

Cited by 124 publications

References 11 publications

Low power, flexible FIR filters in the digital frontend of green radios

Low power, flexible FIR filters in the digital frontend of green radios

Algorithm-based low-power DSP system design: methodology and verification

A New Overlap Save Algorithm for Fast Block Convolution and Its Implementation Using FFT

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