Short-time failure of metal interconnect caused by current pulses

Murguia, James E.; Bernstein, J.B.

doi:10.1109/55.244737

Cited by 42 publications

(11 citation statements)

References 12 publications

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“…A resistor biased at the DC voltage or a pulse follows the differential electrothermal equation [8]: (1) where R 0 and Rs are the initial resistance of the resistor and output impedance of the power supply.…”

Section: B Modelmentioning

confidence: 99%

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A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

Lee

Prabhu

Iyer

et al. 2014

2014 IEEE International Reliability Physics Symposium

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Section: B Modelmentioning

confidence: 99%

“…Up to now, most models to depict the electro-thermal behavior of the interconnection during stress condition are expressed in the form of the current conducted [1]- [3]. However, the transmitting signal in the interconnections and various applications such as the programming of the e-fuse [4] are all applied voltage.…”

Section: Introductionmentioning

confidence: 99%

A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

Lee

Prabhu

Iyer

et al. 2014

2014 IEEE International Reliability Physics Symposium

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show abstract

“…This is the case with TLP for our test patterns with R 0 =10.4 ohms, as temperatures rise to αΔT=2 or 3. TLP has a long history of being used for pulsed metal studies [11,[1][2][3][4][5]. Solving the network for TLP with step V 0 /s and source Zs=50 ohms is fairly simple; the initial power source is…”

Section: B Modeling Of Feedback Phenomenamentioning

confidence: 99%

Achieving electrothermal stability in interconnect metal during ESD pulses

Maloney

Jiang

Poon

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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A feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) pulses predicts a temperature waveform and its stability given a heat source function and a thermoelectric circuit model or thermal impulse response Z(t). The pulse delivery circuit influences those conditions along with materials and layout. Z(t) can be extracted from pre-silicon modeling (e.g., finite element) or from postsilicon transmission line pulse (TLP) response, then applied to any ESD pulse conditions. For metal lines embedded in a patterned matrix of inactive metal lines at adjoining levels, pulses produce temperatures converging to a constant value, so the related time constants allow thermal impedance Z(t) to be deduced and thermal properties of the materials checked.

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“…In the case of a thin metal conductor bonded to an insulating substrate the failure mechanism is the fracturing of the metallic conductor due to Joule heating and mismatched coefficients of thermal expansion between the metal and substrate. For example, common aluminum conductors on silicon dioxide dielectrics will fail with a temperature increase of 300 • C, well below the melting point [142].…”

Section: Joule Heating While Electromigration Damage Is Primarily a Lmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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Short-time failure of metal interconnect caused by current pulses

Cited by 42 publications

References 12 publications

A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

Achieving electrothermal stability in interconnect metal during ESD pulses

Magnetic Random Access Memory for Embedded Computing

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