Shot noise effect on noise source and noise parameter of 10-nm-scale quasi-ballistic n-/p-type MOS devices

Jeon, Jongwook; Kang, Myounggon

doi:10.7567/jjap.55.054102

Cited by 8 publications

(6 citation statements)

References 29 publications

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“…Substituting Equation (6) into Equation (9) and integrating it over the linear region in the channel, the spectral density of induced gate noise is derived as…”

Section: Thermal Noise Modelmentioning

confidence: 99%

“…The individual elements in the equivalent circuit are described in Figure 2. For the prediction of noise performance, the noise parameters such as the minimum noise figure NF min , the noise resistance R n , and the optimum source admittance Y opt = G opt + jB opt are estimated by using R n , G n , G c , and B c as follows [2-7,9] To derive R n , G n , G c , and B c , all the noise sources in Figure 2 are first transferred to the input of noise-free circuit as a series noise voltage and a shunt noise current [2,9]. Next, the correlation matrix is obtained in its chain form, leading to the expressions [2,9]…”

Section: Ann Structure For Noise Performancementioning

confidence: 99%

“…The HF noise sources in MOSFETs include the thermal drain current noise, due to the channel resistance, giving rise to the induced gate noise and the correlation noise [2][3][4][5][6][7]. In the quasi-ballistic regime, with the channel length comparable to the mean free path length of carriers, there is a tunneling current and its shot noise through the source-todrain (SD) potential barrier [8][9][10][11][12][13][14][15][16][17][18]. Moreover, the continuous reduction of gate oxide thickness leads to tremendous gate tunneling currents and noise [2,[19][20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

“…These noise sources must be included to accurately predict the overall noise performance for future CMOS technologies, because significant tunneling current and shot noise are expected at normal operating conditions. However, whenever there is a change in the device structure, a complete physical analysis model is required [9,10,13,22], and the parameter extraction of an HF noise model requires a complicated and difficult process [2][3][4]23]. The accuracy and simplicity of an HF noise model is very important for designing RF circuits.…”

Section: Introductionmentioning

confidence: 99%

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Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

Lee

2021

Electronics

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A physics-informed neural network (PINN) model is presented to predict the nonlinear characteristics of high frequency (HF) noise performance in quasi-ballistic MOSFETs. The PINN model is formulated by combining the radial basis function-artificial neural networks (RBF-ANNs) with an improved noise equivalent circuit model, including all the noise sources. The RBF-ANNs are utilized to model the thermal channel noise, induced gate noise, correlation noise, as well as the shot noise, due to the gate and source-drain tunneling current through the potential barriers. By training a spatial distribution of the thermal channel noise and a Fano factor of the shot noise, underlying physical theories are naturally embedded into the PINN model as prior information. The PINN model shows good capability of predicting the noise performance at high frequencies.

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“…Substituting Equation (6) into Equation (9) and integrating it over the linear region in the channel, the spectral density of induced gate noise is derived as…”

Section: Thermal Noise Modelmentioning

confidence: 99%

Section: Ann Structure For Noise Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

Lee

2021

Electronics

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“…Thus, enhanced g mb from body effect is one of the critical drawback of twin‐well MOS transistor and results in the simultaneous aggravation of power gain and noise figure of the LNA compared to that of tipple‐well option. This is because g mb and substrate resistance ( R sub ) also have effects on the minimum noise figure, NF min , of metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) …”

Section: Lna Design In a Twin‐well Cmos Processmentioning

confidence: 99%

Design optimization of RF low noise amplifier in twin‐well CMOS process

Jhon¹,

Jeon

Kang

2017

Micro & Optical Tech Letters

Self Cite

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18] Hofstetter R, Schmuck H, Heidemann R. Dispersion effects in optical millimeter-wave systems using self-heterodyne method for transport and generation. AbstractThis article presents an optimization technique aiming to improve gain and noise performances simultaneously, through the design of a cost-effective low noise amplifier (LNA) in a mixed-signal CMOS process without an RF triple-well option. To alleviate the inherent body-effect within a twin-well MOS transistor, we applied a transmission-line based source degeneration inductor Ls instead of a conventional spiral in the RF amplifier. In our design, without additional DC-power payment, the gain and noise figures (NF50) improved by 26% and 7.1%, respectively, when compared to the conventional spiral. The proposed LNA was implemented in a 0.18 mm 1-poly 6-metal mixed-signal CMOS process, and achieved a 13.1 dB gain and 2.72 dB noise figure while dissipating 8.76 mA from a 1.4 V supply.K E Y W O R D S low noise amplifier, radio-frequency, twin-well CMOS process

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Analysis of Channel Current Noise in Small Nanoscale Metal Oxide Semiconductor Field Effect Transistors

Jia,

Wei,

Zhu

et al. 2024

Small

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The shrinkage of metal oxide semiconductor field effect transistor (MOSFET) to the small size of the nanoscale results in changes in their channel current noise composition. This paper determines the channel current noise composition of 90 nm MOSFET through experiments, and according to the device material and noise characteristics analysis, the channel current noise of 90 nm and below is obtained, which not only contains thermal noise and suppressed channel shot noise, but also adds suppressed gate tunneling shot noise and cross‐correlation noise. Then, Monte Carlo simulation of 10 nm MOSFET noise is further used to determine the channel current composition of small size nanoscale devices. Subsequently, based on the device structure and fundamental characteristics of channel current noise, the channel current noise model is established. Finally, this model is employed to analyze the relationship between thermal noise, suppressed shot noise, cross‐correlation noise, and channel current noise in relation to bias parameters and device characteristics. The theoretical results are basically consistent with the experimental and the simulated results, and the channel noise increases with the increase of bias voltage. This achievement holds promise for enhancing the operational efficiency, reliability, and lifetime of nanoscale small‐sized MOSFET devices.

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Shot noise effect on noise source and noise parameter of 10-nm-scale quasi-ballistic n-/p-type MOS devices

Cited by 8 publications

References 29 publications

Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

Design optimization of RF low noise amplifier in twin‐well CMOS process

Analysis of Channel Current Noise in Small Nanoscale Metal Oxide Semiconductor Field Effect Transistors

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