Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS

Jannaty, P.; Sabou, F. C.; Le, Son T.; Donato, Marco; Bahar, R. Iris; Patterson, William R.; Mundy, Joseph L.; Zaslavsky, Alexander

doi:10.1109/ted.2011.2180604

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…The two-sided Poisson model has been used in [7] to create a probabilistic framework with the goal of estimating the failure rate due to thermal noise. The framework used predicted data from the ITRS to model a cross-coupled inverter in the 10nm technology node and it was used to investigate the failure-in-time (FIT) due to thermal noise as a function of other parameters such as fabrication process, VDD, and temperature variations.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The framework used predicted data from the ITRS to model a cross-coupled inverter in the 10nm technology node and it was used to investigate the failure-in-time (FIT) due to thermal noise as a function of other parameters such as fabrication process, VDD, and temperature variations. Our work differs from [7] in two ways; we aim to describe the dynamic response of the circuits to voltage transients generated by thermal noise and, while doing so, we extend the study to more complex circuit architectures with multiple logic gates.…”

Section: Background and Related Workmentioning

confidence: 99%

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A fast simulator for the analysis of sub-threshold thermal noise transients

Donato

Bahar

Patterson

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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The gate length of CMOS transistors is continuing to shrink down to the sub-10nm region and operating voltages are moving toward near-threshold and even sub-threshold values. With this trend, the number of electrons responsible for the total charge of a CMOS node is greatly reduced. As a consequence, thermal fluctuations that shift a gate from its equilibrium point may no longer have a negligible impact on circuit reliability. Time-domain analysis helps understand how transient faults affect a circuit and can guide designers in producing noise-resistant circuitry. However, modeling thermal noise in the time-domain is computationally very costly. Moreover, small fluctuations in electron occupation introduce time-varying biasing point fluctuations, increasing the modeling complexity. To address these challenges, this paper introduces a new approach to modeling thermal noise directly in the time domain by developing a series of stochastic differential equations (SDE) to model various transient effects in the presence of thermal noise. In comparisons to SPICE-based simulations, our approach can provide 3 orders of magnitude speedup in simulation time, with comparable accuracy. This simulation framework is especially valuable for detecting rare events that could translate into fault-inducing noise transients. While it is computationally infeasible to use SPICE to detect such rare events due to thermal noise, we introduce a new iterative approach that allows detecting 6σ events in a matter of a few hours.

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Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

A fast simulator for the analysis of sub-threshold thermal noise transients

Donato

Bahar

Patterson

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

Self Cite

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“…A queue representation of the output current fluctuations was then used for computing the probability of a soft error in subthreshold operation. More recently, similar approaches [8][9] [10] have been used for modeling the error rate of flip-flops both in sub-threshold and above-threshold operation for end-of-roadmap CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

“…While this has led to some interesting results, we still lack a time-domain framework necessary for capturing the dynamic response to noise in nonlinear circuits. In this paper, we extend the same unified model for thermal and shot noise [8][9] [10] to the time domain by modeling the noise fluctuations as a stochastic process.…”

Section: Introductionmentioning

confidence: 99%

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits

Donato

Bahar

Patterson

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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Noise analysis in nonlinear logic circuits requires models that take into account time-varying biasing conditions. When considering thermal noise, which moves the circuit away from its equilibrium point, a correct modeling approach has to go beyond the additive white Gaussian noise (AWGN) used in classical noise analysis. Even when accurate models are available, running standard MonteCarlo simulations that will expose rare soft errors may still be computationally prohibitive. Probabilistic methods are often preferred for estimating the failure rate. However, these approaches may not provide any insight about the dynamic response to noise events. In this paper, we target both problems in the sub-threshold logic application domain. We first provide a time-domain model for fundamental, technology-independent thermal noise in sub-threshold circuits. Then, we use this model to generate noise input files for SPICE transient analysis. The effectiveness of the approach is demonstrated using 7nm FinFET predictive technology models (PTM) for an inverter and a NAND gate.

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