Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits

“…Previous works [12][8] [9][10] that have been based on the same two-sided Poisson noise have used inverters or flip-flops. In all these cases, the output noise results from the contribution coming from two transistors.…”

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

“…Advances in nanofabrication technology have opened up the possibility of surpassing the ultimate performance limits of modern CMOS devices [1,2]. However, the sub-10 nm channel length in MOSFETs gives rise to tunneling current and associated shot noise through the source-to-drain (SD) potential barrier [3][4][5][6][7][8][9][10][11][12][13][14][15]. With the downscaling of device dimensions, the continuous reduction in gate oxide thickness leads to enormous gate tunneling currents and noise [16][17][18][19][20][21][22][23].…”

“…Therefore, the off-state currents, from which the static power dissipated by MOSFETs originates, are enhanced by the direct tunneling current through the SD potential and gate oxide in the subthreshold region and consequently prevent low voltage/power operation [5][6][7]. In addition, the miniaturization of nanoscale CMOS logic devices has made the quantum nature of current flow more pronounced, leading to higher fault rates due to shot noise in the subthreshold region [14]. These factors set fundamental limits on future CMOS technologies, because significant tunneling currents and shot noise are expected under normal operating conditions.…”

“…These factors set fundamental limits on future CMOS technologies, because significant tunneling currents and shot noise are expected under normal operating conditions. The intriguing properties of shot noise, which have been extensively studied in mesoscopic devices, should manifest themselves in sub-10 nm MOSFETs, as the devices enter the ballistic transport regime [9][10][11][12][13][14][15]. However, analytical and highly predictive noise models in ballistic MOSFETs for circuitlevel simulation are still lacking [10][11][12].…”

“…However, analytical and highly predictive noise models in ballistic MOSFETs for circuitlevel simulation are still lacking [10][11][12]. Although the need for a unified model of shot noise in the SD and gate tunneling current arises frequently in quasi-ballistic MOSFET operation, these currents are typically treated separately for each case [9][10][11][12][13][14][15][21][22][23]. In this work, a single unified analytical expression is presented for the SD and gate tunneling currents and the associated shot noise, emphasizing their similarities and differences.…”