Shuttle mask floorplanning

Xu, Gang; Tian, Ruiqi; Wong, Martin D. F.; Reich, Alfred J.

doi:10.1117/12.517568

Cited by 23 publications

(18 citation statements)

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“…Experiments on industry test cases show that our methods outperform significantly previous methods in the literature as well as floorplans manually designed by experienced engineers. Our methods can also be extended to handle additional constraints such as die-alignment constraints imposed by the use of die-to-die mask inspection [13] by merging two copies of a die in a single "superdie." With ongoing work, we investigate the use of multiple die copies on the reticle and multilayer reticles for further reductions in the manufacturing cost of given die production volumes.…”

Section: Discussionmentioning

confidence: 99%

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Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction

Chiang

Kahng²,

Sinha³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The aggressive scaling of very large-scale integration feature size and the pervasive use of advanced reticle enhancement technologies lead to dramatic increases in mask costs, pushing prototype and low-volume production designs to the limit of economic feasibility. Multiproject wafers (MPWs), or "shuttle" runs, provide an attractive solution for such designs by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce complexities that are not encountered in typical single-project wafers. Recent works on wafer dicing adopt one or more of the following assumptions to reduce problem complexity: 1) equal production volume requirement for all designs; 2) same dicing plan used for all wafers or for all rows/columns of reticle images on a wafer; 3) unrealistic wafer models such as a rectangular array of projections; and 4) fixed wafer shot-map. Although using one or more of the aforementioned assumptions makes the problem solvable, the performance of the solutions is degraded. In this paper, a comprehensive MPW flow aimed at minimizing the number of wafers needed to fulfill given die production volumes is proposed. The proposed flow includes two main steps: 1) multiproject reticle floorplanning and 2) wafer shot-map and dicing plan definition. For each of these steps, improved algorithms are proposed as follows. The proposed reticle floorplanner uses a hierarchical quadrisection combined with simulated annealing to generate "diceable" floorplans, observing given maximum reticle sizes. The proposed dicing planner allows multiple side-to-side dicing plans for different wafers and different reticle projection rows/columns within a wafer and further improves the dicing yield by partitioning each wafer into a small number of parts before individual die extraction. A wafer shot-map definition heuristic is also proposed in order to fully utilize round wafer real estate by extracting the maximum number of functional dies from both fully and partially printed reticle images. Experiments on industry test cases show that the proposed methods outperform significantly not only previous methods in the literature but also reticle floorplans manually designed by experienced engineers.

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Section: Discussionmentioning

confidence: 99%

“…Xu et al [13] studied the MPW mask floorplanning under die-alignment constraints imposed by the use of die-to-die mask inspection. All these approaches assume that all dies can be obtained, which is impractical for current side-to-side wafer-dicing technology.…”

mentioning

confidence: 99%

Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction

Chiang

Kahng²,

Sinha³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Xu et al [11] studied the MPW mask floorplanning under die-alignment con straints imposed by the use of die-to-die mask inspec tion. A grid-packing formulation for MPW mask floor planning was proposed in [2], where the objective is to find a minimum area grid floorplan with at most one die per grid cell.…”

Section: Introductionmentioning

confidence: 99%

Efficient design and analysis of robust power distribution meshes

Gupta

Kahng

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling leads to dramatic increases in mask costs. In response to this trend, mUltiple project wafers (MPW) have been proposed as an effective technique for sharing the cost of mask tooling among Up to tens of prototype and low volume de signs. Previous works on MPW reticle design and dicing have focused on the simple scenario in which production volumes are known a priori. However, this scenario does not apply for low-and medium-volume production, in which mask manufacturing is typically started when only rough estimates of future customer demands are avail able. In this paper we initiate the study of MPW use for production under demand uncertainty and propose efficient algorithms for two main optimizations that arise in this context: reticle design under demand uncertainty and on demand wafer dicing. Preliminary experiments on simulated data show that our methods help reducing the cost overheads incurred by demand uncertainty, yielding solutions with a cost close to that achievable when a priori knowledge of production volumes is available.

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“…However, some of the previous works [1,2] did not consider the side-to-side dicing technology. Some of them [1,2,3,4,5] did not aim at maximizing the wafer utilization but aim at minimizing reticle area. Kahng [6] revisited the MPW problem and tried to minimize the number of wafers used.…”

Section: Figure 1: a Multi-project Wafermentioning

confidence: 99%