Shuttle mask floorplanning with modified alpha-restricted grid

Ching, Royce L.S.; Young, Evangeline F. Y.

doi:10.1145/1127908.1127930

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…Chen and Mak (2006) propose a method to solve a reticle floorplanning problem for chips using a different number of metal layers. Ching and Young (2006) define a special type of grid, called modified alpha-restricted grid, to reduce the size of the solution space for grid floorplan.…”

Section: Related Work For Rfpmentioning

confidence: 99%

Reticle Floorplanning and Simulated Wafer Dicing for Multiple-Project Wafers by Simulated Annealing

Lin¹,

Wu²,

Tsai³

2008

Simulated Annealing

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Section: Related Work For Rfpmentioning

confidence: 99%

Reticle Floorplanning and Simulated Wafer Dicing for Multiple-Project Wafers by Simulated Annealing

Lin¹,

Wu²,

Tsai³

2008

Simulated Annealing

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“…Kahng et al [2006] proposed an MPW dicing methodology to minimize wafer use when production volumes are uncertain. Ching and Young [2006] defined a special type of grid, called the modified alpha-restricted grid, to reduce the solution space size for grid floorplanning.…”

Section: Introductionmentioning

confidence: 99%

“…They are compatible if they are not in dicing conflict with each other. Conversely, shelf packing , grid floorplanning [Andersson et al 2005;Kahng and Reda 2004;Chen and Mak 2006;Ching and Young 2006], or hierarchical quadrisection methods [Kahng et al 2005] perform chip placement subject to a controlled amount of dicing conflict. A floorplan obtained using these methods may not be as compact, but this does not mean that more wafers will be required because fewer dice will be destroyed due to a controlled amount of dicing conflict.…”

Section: Introductionmentioning

confidence: 99%

Chip placement in a reticle for multiple-project wafer fabrication

Lin

Tsai

2008

ACM Trans. Des. Autom. Electron. Syst.

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Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among chips with large-volume requirements while minimizing reticle dimensions. Our mixed-integer linear programming models with VOCO are too complex to render good solutions for large test cases. Our B*-tree with VOCO and HQ with VOCO use 16%∼29% fewer wafers and 8%∼19% less reticle area than the hierarchical quadrisection (HQ) method proposed by Kahng et al. [2005]

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