SiC MOSFET design considerations for reliable high voltage operation

Losee, Peter A.; Bolotnikov, Alexander; Yu, Libing; Dunne, Greg; Esler, David; Erlbaum, J.; Rowden, Brian; Gowda, Arun; Halverson, Adam F.; Ghandi, Reza; Sandvik, Peter; Stevanovic, Ljubisa; Hristov, R.

doi:10.1109/irps.2017.7936254

Cited by 29 publications

(8 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast, a maximum electric field of 3.6 MV/cm is observed at the edge of the gate electrode for the SG-MOSFET structure. Both values are below 4 MV/cm considered acceptable from reliability considerations [17]. This is an important observation from this work indicating that the Split-Gate concept can be applied to 2.3 kV 4H-SiC power MOSFETs.…”

Section: Device Structure and Analysismentioning

confidence: 53%

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

Agarwal

Han

Baliga

2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit (HF-FOM) of the 2.3 kV SG-MOSFETs were experimentally verified to be a factor of 1.8x better than that of the conventional MOSFETs with no difference in specific on-resistance.INDEX TERMS 4H-SiC, 2.3 kV devices, accumulation channel, C gd , planar-gate MOSFET, Q gd , R on,sp , silicon carbide, split-gate.

show abstract

Section: Device Structure and Analysismentioning

confidence: 53%

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

Agarwal

Han

Baliga

2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…A standard stripe-type cell layout, which is similar to one reported in Ref. [7], was adopted. In the stripe geometry, channel implantation was performed twice to make channels on both sides of the stripe.…”

Section: Methodsmentioning

confidence: 99%

Fabrication and Characterization of 3.3-kV SiC DMOSFET with Self-Aligned Channels Formed by Tilted Ion Implantation

Morikawa

Sato

Shima

2019

MSF

View full text Add to dashboard Cite

SiC DMOSFET with self-aligned channels was fabricated and characterized. The process features self-aligned channel formation by utilizing tilted ion implantation. We confirmed that channel areas were successfully formed along both sides of the stripe cell. Electrical measurements revealed that the characteristics of the fabricated DMOSFET chips had sufficiently high blocking voltage and moderate values of threshold voltage and on-state resistance. These experimental results show the proposed process can be an easy option for fabrication of SiC DMOSFET.

show abstract

“…High voltage and current are applied simultaneously to the devices when the gate-drain capacitance (C GD ) is being charged [5,6]. Several studies to improve the switching characteristics of SiC MOSFETs by reducing the Q GD have been reported [7][8][9][10][11][12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

“…In the case of the device with the tapered buffer oxide, the maximum electric field at the gate oxide in the off state (E ox,max ) of the device is highly dependent on the angle of the tapered buffer oxide [14]. Several studies that have investigating the gate reliability of SiC MOSFETs using an analysis of time dependent dielectric breakdown have reported that SiC MOSFETs have reliable electrical characteristics when the E ox,max has been designed below 3 MV/cm [16][17][18]. Therefore, it is necessary to develop the devices for low E ox,max as well as for low Q GD .…”

Section: Introductionmentioning

confidence: 99%

Design of a 1.2 kV SiC MOSFET with Buried Oxide for Improving Switching Characteristics

Yoon,

Seok

2024

Electronics

View full text Add to dashboard Cite

The 1.2 kV SiC MOSFET with a buried oxide was verified to be effective in improving switching characteristics. It is crucial to reduce the gate–drain charge (QGD) of devices to minimize switching loss (Etotal). The SiC MOSFET with a split gate and device with a buffered oxide have been proposed by previous studies to reduce the QGD of the devices. However, both devices have a common issue of the concentration of the electric field at the gate oxide. In this paper, we propose the 1.2 kV SiC MOSFET with a buried oxide to reduce the QGD and suppress the electric field crowding effect at the gate oxide. We analyzed the specific on-resistance (Ron,sp), QGD and the maximum electric field at the gate oxide in the off state (Eox,max) according to the width (WBO) and thickness of the buried oxides (TBO). The device with the buried oxide, under optimal conditions, showed lower Eox,max and Etotal without significant increase in Ron,sp in comparison to the device with a conventional structure. These results indicate that the buried oxide can improve the switching characteristics of 1.2 kV SiC MOSFETs.

show abstract

SiC MOSFET design considerations for reliable high voltage operation

Cited by 29 publications

References 8 publications

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

Fabrication and Characterization of 3.3-kV SiC DMOSFET with Self-Aligned Channels Formed by Tilted Ion Implantation

Design of a 1.2 kV SiC MOSFET with Buried Oxide for Improving Switching Characteristics

Contact Info

Product

Resources

About