Side-Channel Analysis of the Xilinx Zynq UltraScale+ Encryption Engine

Abstract

The Xilinx Zynq UltraScale+ (ZU+) is a powerful and flexible System-on- Chip (SoC) computing platform for next generation applications such as autonomous driving or industrial Internet-of-Things (IoT) based on 16 nm production technology. The devices are equipped with a secure boot mechanism in order to provide confidentiality, integrity, and authenticity of the configuration files that are loaded during power-up. This includes a dedicated encryption engine which features a protocol-based countermeasure against passive Side-Channel Attacks (SCAs) called key rolling. The mechanism ensures that the same key is used only for a certain number of data blocks that has to be defined by the user. However, a suitable choice for the key rolling parameter depends on the power leakage behavior of the chip and is not published by the manufacturer. To close this gap, this paper presents the first publicly known side-channel analysis of the ZU+ encryption unit. We conduct a black-box reverse engineering of the internal hardware architecture of the encryption engine using Electromagnetic (EM) measurements from a decoupling capacitor of the power supply. Then, we illustrate a sophisticated methodology that involves the first five rounds of an AES encryption to attack the 256-bit secret key. We apply the elaborated attack strategy using several new Deep Learning (DL)-based evaluation methods for cryptographic implementations. Even though we are unable to recover all bytes of the secret key, the experimental results still allow us to provide concrete recommendations for the key rolling parameter under realistic conditions. This eventually helps to configure the secure boot mechanism of the ZU+ and similar devices appropriately.

Enhancing non-profiled side-channel attacks by time-frequency analysis

“…In recent years, some hardware vendors have considered designing countermeasures for commercial crypto products to resist various physical attacks. For instance, Xilinx Zynq Ultracale+ (ZU+) Encryption Engine adopts proprietary countermeasures to resist SCA (Hettwer et al 2021). In this case, adversaries need to extract the secret key within limited data.…”

“…Besides, some newest crypto products also adopt some specific protections to render adversaries' attack capability. For example, Zynq Ultracale+ (ZU+) Encryption Engine employs a key rolling scheme and Rivest Shamir Adleman (RSA) authentication to resist side-channel attacks (Hettwer et al 2021). Similar to NIST CTR_DRBG specification, ZU+ utilizes key rolling scheme in AES-CTR encryption.…”

FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream Level

“…However, the use of key-rolling comes with a performance-security trade-off. In [17], after thorough experimentation, it was found that to be protected against current side-channel attacks, the key-rolling factor has to be set between 20 and 30. This imposes a considerable performance overhead.…”

Trojan Awakener: Detecting Dormant Malicious Hardware Using Laser Logic State Imaging

“…Most securitycritical FPGAs rely on bitstream encryption and authentication to avoid such Trojan insertions. However, these protection schemes have shown to be vulnerable to various physical [3]- [6] and mathematical attacks [7], leaving them susceptible to tampering. Consequently, in critical applications, where the chip is deployed in an untrusted field or could be accessed by untrusted parties, it should be possible to check the integrity of the hardware.…”

“…On the other hand, due to their reconfigurability, they provide the possibility for malicious modifications even after the product has been shipped to the user. It has been shown that the key used for encrypting the bitstream on recent SRAM-based FPGAs can be extracted using SCA techniques [3]- [6]. With the extracted key at hand, the bitstream can be decrypted, modified, and stored as a replacement for the original bitstream [17].…”