Side-channel leakage assessment metrics and methodologies at design cycle: A case study for a cryptosystem

Bokharaie, Vahhab Samadi; Jahanian, Ali

doi:10.1016/j.jisa.2020.102561

Cited by 3 publications

(1 citation statement)

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“…Hence, evaluating the resistance of cryptographic implementations against power analysis attacks has become an important issue in the field of information security [1]. The evaluating process aims to judge whether there is side-channel leakage within a limited time [2]. Previously, the evaluating process was executed utilizing all kinds of known side-channel analysis attacks, with a successful key recovery by any attack indicating that there is leakage.…”

Section: Introductionmentioning

confidence: 99%

An Efficiency–Accuracy Balanced Power Leakage Evaluation Framework Utilizing Principal Component Analysis and Test Vector Leakage Assessment

Zhang¹,

Yan²,

Liu³

et al. 2022

Electronics

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The test vector leakage assessment (TVLA) is a widely used side-channel power leakage detection technology which requires evaluators to collect as many power traces as possible to ensure accuracy. However, as the total sample size of the power traces increases, the amount of redundant information will also increase, thus limiting the detection efficiency. To address this issue, we propose a principal component analysis (PCA)-TVLA-based leakage detection framework which realizes a more advanced balance of accuracy and efficiency. Before implementing TVLA to detect leakage, we project the original power data onto their most significant feature dimensions extracted by the PCA procedure and screen power traces according to the magnitude of their corresponding components in the variance of the projection vector. We verified the overall performance of the proposed framework by measuring the detection capability and efficiency with t-values and the required time, respectively. The results show that compared with similar existing schemes, under the best circumstances, the proposed framework decreases the t-value by 4.3% while saving time by 25.2% on the MCU platform and decreases the t-value by 2.4% while saving time by 38.0% on the FPGA platform.

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Section: Introductionmentioning

confidence: 99%