Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs

Hållstedt, Julius; Hellström, Per‐Erik; Radamson, Henry H.

doi:10.1016/j.tsf.2008.08.134

Cited by 34 publications

(22 citation statements)

References 6 publications

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“…Sidewall transfer lithography (STL) technique with an anisotropic dry etch was applied to create Si fins with 110 nm height and 15 nm width [10]. In this step, Si 3 N 4 /SiO 2 spacers were used as hard mask for plasma-etch of the Si.…”

Section: Methodsmentioning

confidence: 99%

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Radamson

Luo

Qin

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10 20 cm −3 . The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO 2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

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Section: Methodsmentioning

confidence: 99%

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Radamson

Luo

Qin

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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“…The nanowires were defined with STL [17] using I-line lithography. The key points for reliable and reproducible definition of SiNW using STL are: good control of the thickness of deposited layers, conformal deposition of the sidewall material, anisotropic dry etching and selective etching for removing material.…”

Section: Fabricationmentioning

confidence: 99%

“…The key points for reliable and reproducible definition of SiNW using STL are: good control of the thickness of deposited layers, conformal deposition of the sidewall material, anisotropic dry etching and selective etching for removing material. In previous work [17,18], several tools were employed for deposition and dry etching in the STL process. In this work, we have implemented the STL process in a cluster tool equipped with chambers for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD).…”

Section: Fabricationmentioning

confidence: 99%

Silicon nanowires integrated with CMOS circuits for biosensing application

Jayakumar

Asadollahi

Hellström

et al. 2014

Solid-State Electronics

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a b s t r a c tWe describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N 2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

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“…By removing the sacrificial layer, the spacer can be used as a hard mask to define structures in the underlying layers. The spacer technique has been applied in order to fabricate fin field effect transistors (Fin FETs) with shorter gate length and higher performance than lithographically defined MOS FETs [15]- [18]. Devices made with the spacer technique have been deployed in other fields as well, such as optical applications [19], high-frequency transistors [20] and biosensing [21].…”

Section: A Spacer Technologymentioning

confidence: 99%

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa

Cerofolini

Micheli

et al. 2011

IEEE Trans. Nanotechnology

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Abstract-In this paper, we demonstrate the ability of the multispacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution andCMOS processing steps. We characterize single spacers operating as poly-Si nanowire field effect transistors . We demonstrate also the possibility to lay a spacer perpendicularly to a set of parallel spacers in a crossbar fashion. The extrapolated cross-point density from the small 4 × 1-array is in the range of 10 10 cm −2 . We discuss the applications of this technique to improve the density of previously reported poly-SiNW memories and as a future framework for nanowire crossbars and decoders. Then we analyze the limitations and costs of the proposed technique.

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Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs

Cited by 34 publications

References 6 publications

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Silicon nanowires integrated with CMOS circuits for biosensing application

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

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