SiGe HBT BiCMOS FPGAs for fast reconfigurable computing

Goda, Bryan; McDonald, J. F.; Carlough, S.R.; Krawczyk, T.W.; Kraft, R.P.

doi:10.1049/ip-cdt:20000468

Cited by 17 publications

(6 citation statements)

References 1 publication

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“…Each CLB includes two identical slices, one of which is shown in Figure 2 The basic ideas for designing the Virtex CLB can be applied for any other FPGAs. These ideas include: (1) Use the interface circuit between the SRAMs and CML circuits [3]; (2) Exploit the higher density of CMLs and merge several elements in the logic cell into one CML circuit; (3) By setting high current for CML circuits in the fast carry chain (vertical path) and low current for all other CMLs, one can easily speed up the addition without incurring high power dissipation; (4) Turn off the standby parts to save power.…”

Section: Circuit Design Considerationsmentioning

confidence: 99%

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Multi-GHz SiGe design methodologies for reconfigurable computing

Zhou

McDonald

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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A high-speed and low-power Field Programmable Gate Array (FPGA) is the dream of digital designers. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz FPGAs [3,4]. In the past, high static power consumption discouraged the significant scale-up of bipolar FPGAs. This paper details new ideas to reduce power and layout area in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize novel serial dual configuration planes to achieve an efficient programmability. In addition, new layout techniques are developed to reduce the bipolar areas. Several SiGe FPGA test chips based on Xilinx 6200 and Virtex Configurable Logic Blocks (CLBs) have been fabricated for demonstration.

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Section: Circuit Design Considerationsmentioning

confidence: 99%

“…The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz FPGAs [3,4]. In the past, high static power consumption discouraged the significant scale-up of bipolar FPGAs.…”

mentioning

confidence: 99%

Multi-GHz SiGe design methodologies for reconfigurable computing

Zhou

McDonald

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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“…The interconnection networks are completely programmable and are used to establish connection either between CLBs or between CLBs and I/O blocks. The I/O blocks are also configurable and are used to configure pins of the chip as input, output or bidirectional pins [13,14]. FPGA chips are not used solely for developing applications.…”

Section: Fpga Chipsmentioning

confidence: 99%

A Data Path Design Tool for Automatically Mapping Artificial Neural Networks on to FPGA-Based Systems

Şahin¹,

Sarıtekin²

2016

Journal of Electrical Engineering and Technology

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-Artificial Neural Networks (ANNs) are usually implemented as software running on general purpose computers. On the other hand, when software implementations do not provide sufficient performance, ANNs are implemented as hardware on FPGA based systems for performance enhancement. Mapping ANNs to FPGAs is a time consuming and error prune process. In this study, a novel data path design tool, ANNGEN, has been proposed to help automate mapping ANNs to FPGA based systems. ANNGEN accepts ANN definitions in a NetList form. First, it parses and analyzes given NetList. Second, it checks the availability of the neurons. If all the neurons required by the NetList are available in its neuron Library, ANGENN performs the design procedure and produces VHDL code for the given NetList. ANNGEN has been tested with several different test cases, and it is observed that it is able to successfully generate VHDL codes for given ANN NetLists. Our practice with ANNGEN has showed that it effectively shortens the time required for implementing ANNs on FPGAs. It also eliminates the need for expert people. Additionally, ANNGEN produces error free code; thus, the debugging stage is also eliminated.

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“…Since the number of trees in both the combinational and sequential paths have been reduced, the propagation delay is also reduced. The propagation delay for the earlier CLB was 100 ps [1] and that of the new CLB is around 52 ps.…”

Section: Design Descriptionmentioning

confidence: 99%