Abstract-HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of rf lines and resistance of dc bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g. ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of highspeed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.Index Terms-Closed-cycle refrigerator, Cryopackaging, Digital Receiver, Cryoelectronics, Thermal Management, Broadband Digital Link. I. INTRODUCTIONWhile the superior performance of superconducting digital electronics (SCE) has been demonstrated, no significant market for these has emerged so far. There are several reasons for this lack of commercial success: (1) until recently, no commercial application with a significant market demanded a level of performance that can only be attained with SCE, (2) almost all demonstrations have used liquid helium as a cryogen which is unacceptable for most commercial products, (3) ultra-fast, low-level signals used in SCE are incompatible with room temperature electronics (RTE). Recently, the situation has changed dramatically. The explosive demand for information bandwidth in the commercial and military wireless communication market has created a unique opportunity for superconducting digital electronics in software defined radio (SDR). Reliable, reasonably compact, and affordable 4 K cryocoolers are now available and have been used commercially by HYPRES to cool the Josephson primary voltage standard chip. Finally, improvements in cooled semiconductor low-noise, broadband amplifiers make it feasible to interface SCE with RTE in a manner that is transparent to the user.In this article, we focus on small-scale SCE digital systems, consisting of a single integrated circuit (IC) or a few ICs on a multi-chip module (MCM), rather than large-scale digital systems. The architecture of a small-scale digital system, such as a digital-RF transceiver for wireless communications [1] is shown in Fig. 1. The superconductor ICs, assumed to be Nb RSFQ circuits, need to be cooled to 4-5 K, which requires a closed-cycle refrigerator (CCR) or cryocooler with at least two temperature stages. The hig...

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were neverpossible using CMOS as the basic device. People were able fo achieve frequencies in the range of 70-250 MHz using CMOS. The availabili~y of Silicon Gemanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reponed by B.S. Goda [ I . 21 using SiGe 5HP technology. Howeve,: in order to scale up FPGAs significantly, a serious power management scheme musf be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CL.B) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novelpower management scheme is implemenred which allows the FPGA to operate at multiple modes: fast, non-critical. slow and OB: The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

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