SiGe heterostructure field-effect transistor using V-shaped confining potential well

Analogue micropower FET techniques review

“…The concept was extended by the addition of a gateoxide as a barrier to prevent high leakage currents via the gate contact [62] and by the growth of MBE layers on relaxed SiGe buffer layers (termed a virtual substrate), an innovation that offers the possibility to grow thin (∼8 nm) strained Si channels in SiGe. N-type HMOSFET devices, grown by fabricating the active n-type layers on relaxed p-type SiGe buffer layers, were presented originally in [63,64] and more recently in [16,19,[65][66][67][68][69][70][71]. Burying the channel (strained or unstrained) further from the gate was reported to reduce surface carrier trapping, caused by the high density of interface states at the oxide/SiGe interface, and increase the mobility of the channel-confined carriers at the expense of a decrease in transconductance due to the channel's greater distance from the applied gate voltage [72][73][74].…”

Improved performance of SiGe doped-channel field-effect transistor using inductively coupled plasma etch

“…An alternative way to minimize these problems is to increase the effective carrier confinement. Our previous investigation of δ-doped-channel FETs [8,9] revealed an increase in device linearity and a reduction in gate leakage current. In this paper, SiGe doped-channel field-effect transistors with ICP mesa etching are proposed.…”