Signal correction for combinational automation devices on the basis of Boolean complement with control of calculations by parity

Abstract

Simpler than known structure of the system with error correction in calculations is proposed based on duplication and triplication of blocks with majority principle of choosing the values of signals. It is advisable to use the new fault-tolerant structure for automation devices with combinational logic. In fault-tolerant structure synthesis, the parity method is used to establish the fact of a fault in the main logic unit and the logical complement method is used determine incorrectly calculated output functions and to generate signals for their correction. The method also allows to adjust the values of incorrectly calculated functions. Structural diagram and description of error correction system are given. The synthesis algorithm of control equipment is described with minimization of the technical implementation complexity. The experiment results with control combinational circuits are given, confirming the high efficiency of proposed system structure with error correction.

Boolean-Complement Based Fault-Tolerant Electronic Device Architectures

“…Experiments with combinational benchmarks show that in practice it is possible to achieve a considerable reduction in the complexity of the technical implementation of a fault-tolerant circuit by using new architectures in comparison with the known DMR and TMR architectures. For example, it is shown in [15,16] that one can simplify architectures up to 25-30% in comparison with DMR architectures and up to 40-45% in comparison with the TMR architecture. In this case, it is possible to achieve high signal-correction rates without changing the architectures of source objects.…”

“…In [15,16], fault-tolerant architectures for combinational circuits are considered. They are based on the use of the well-known Boolean complement method [17][18][19].…”

Transitions weight-based sum code for the digital computing devices synthesis

“…5). A similar structure, when used to checking computations of parity codes, is described in [26], and [27,28].…”

“…In this case, checking calculations is carried out at the diagnostic object F (x) outputs. Unlike the structure considered in [26], where the built-in control circuit is synthesized by the parity method [18], in the generalized structure, the code control allows detecting a much larger number of errors at the outputs of the F (x) block. The CED circuit outputs generate a signal of no error…”

“…5. The correction circuit structure based on the T q m -code values at the CED circuit two-rail outputs coincide, indicating errors in the calculations.The structure shown in Fig.5, is not protected from faults in the signal correction gates unit; however, the traditional structure with majority signal correction has the same drawback[26]. In practice, this drawback is levelled using highly reliable gates in the signal correction unit synthesis with low failure rates and internal redundancy and implemented in completely self-checking devices.…”