Signal Integrity Flow for System-in-Package and Package-on-Package Devices

Pulici, Paolo; Vanalli, G.P.; Dellutri, M.; Guarnaccia, D.; Iacono, F. Lo; Campardo, G.; Ripamonti, G.

doi:10.1109/jproc.2008.2007469

Cited by 17 publications

(8 citation statements)

References 22 publications

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“…where (9) and the subscript " A " indicates the previous signal. Similarly, the present signal can be formulated as …”

Section: Input Test Patterns In a Single Linementioning

confidence: 99%

“…Two distinct PRBS input signals are generated with a 16-stage linear feedback shift register (LFSR) composed of [16,13,9,6] and [16,10,7,4] feedback taps.…”

Section: Verification Of the Proposed Techniquementioning

confidence: 99%

“…In high-speed digital systems, signal integrity exacerbation due to interconnect lines significantly limits circuit performance [1][2][3][4][5][6][7][8][9]. Thus, the signal integrity verification of interconnect lines has become an integral part of the system design.…”

Section: Introductionmentioning

confidence: 99%

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Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

Lee¹,

Kim²,

Eo³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

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“…where (9) and the subscript " A " indicates the previous signal. Similarly, the present signal can be formulated as …”

Section: Input Test Patterns In a Single Linementioning

confidence: 99%

“…Two distinct PRBS input signals are generated with a 16-stage linear feedback shift register (LFSR) composed of [16,13,9,6] and [16,10,7,4] feedback taps.…”

Section: Verification Of the Proposed Techniquementioning

confidence: 99%

See 1 more Smart Citation

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

Lee¹,

Kim²,

Eo³

2013

JSTS:Journal of Semiconductor Technology and Science

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“…In the context of modern digital base-band processors for mobile applications, the most common package structures adopted in commercial devices are reported in figure 1, namely single-die fcBGA, multiple-dies SiP (System-in-Package), PoP (Package-on-Package) and PiP (Package-in-Package). For these devices, packages do not only provide a mechanical support and a first-level of interconnection towards the outer world, but realize also internal chip-to-chip communication links [4]. The routing of signals and power distribution networks (PDNs) is highly dense, and the risk of performance degradation is increased due to potential mutual interferences between different portions of the system.…”

Section: Introductionmentioning

confidence: 99%

Macromodel-based Signal and Power Integrity simulations of an LP-DDR2 interface in mSiP

Signorini

Grivet-Talocia

Stievano

et al. 2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Signal and Power Integrity (SI/PI) analyses assume a paramount importance to ensure a secure integration of highspeed communication interfaces in low-cost highly-integrated System-in-Package(s) (SiP) for mobile applications. In an iterative fashion, design and time-domain SI/PI verifications are alternated to assess and optimize system functionality. The resulting complexity of the analysis limits simulation coverage and requires extremely long runtimes (hours, days). In order to ensure post-silicon correlation, electrical macromodels of Package/PCB parasitics and high-speed I/Os can be generated and included in the testbenches to expedite simulations. Using as example an LP-DDR2 memory interface to support the operations of a mobile digital base-band processor, we have developed and applied a macromodelling flow to demonstrate simulation run-time speedup factors (x1200+), and enable interface-level analyses to study the effects of Package/PCB parasitics on signals and PDNs, as well as the corresponding degradation in the timing budget.

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“…However, since interconnect lines cannot be scaled down as much as transistors, interconnect latency and bandwidth may dominate system performance [5]- [7]. In particular, signal integrity exacerbation due to interconnect lines may play a decisive role in the performance of high-speed digital systems [8], [9]. Thus, the signal integrity verification of interconnect lines becomes an integral part of system design.…”

Section: Introductionmentioning

confidence: 99%

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Kim

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, a new efficient and accurate analytical eye-diagram determination technique for interconnect lines is presented. The simplest input test signal model for the intersymbol interference analysis of high-speed data links is mathematically formulated. Since input test patterns for eye boundaries are determined analytically, it is considered very convenient and efficient. The proposed technique shows excellent agreement with the SPICE-based simulation in both eye height and jitter, i.e., within 5% error for nondiscontinuous data paths and 10% error for discontinuous data paths. The method is much more computation-time-efficient than the pseudorandom bit sequence-based SPICE simulation in the order of magnitude.Index Terms-Eye diagram, intersymbol interference (ISI), jitter, signal integrity, transmission line.

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Signal Integrity Flow for System-in-Package and Package-on-Package Devices

Cited by 17 publications

References 22 publications

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

Macromodel-based Signal and Power Integrity simulations of an LP-DDR2 interface in mSiP

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

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