Silencing Hardware Backdoors

Abstract

Abstract-Hardware components can contain hidden backdoors, which can be enabled with catastrophic effects or for ill-gotten profit. These backdoors can be inserted by a malicious insider on the design team or a third-party IP provider. In this paper, we propose techniques that allow us to build trustworthy hardware systems from components designed by untrusted designers or procured from untrusted third-party IP providers.We present the first solution for disabling digital, designlevel hardware backdoors. The principle is that rather than try to discover the malicious logic in the design -an extremely hard problem -we make the backdoor design problem itself intractable to the attacker. The key idea is to scramble inputs that are supplied to the hardware units at runtime, making it infeasible for malicious components to acquire the information they need to perform malicious actions.We show that the proposed techniques cover the attack space of deterministic, digital HDL backdoors, provide probabilistic security guarantees, and can be applied to a wide variety of hardware components. Our evaluation with the SPEC 2006 benchmarks shows negligible performance loss (less than 1% on average) and that our techniques can be integrated into contemporary microprocessor designs.

VeriTrust: Verification for Hardware Trust

“…There have been some recent research efforts to achieve the above objectives via design obfuscation and/or isolation [19][20][21][22]. These solutions facilitate to mitigate some HT threats, but the associated design cost is quite high and there is no guarantee that ICs would be HT-free with these design methodologies.…”

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

“…This is basically an agreement between a SoC integrator and a 3PIP vendor on a pre-defined set of properties which can be verified by SoC integrator. Waksman et al [10] instead of discovering the malicious logic in the design, which they believe-is an extremely hard problem-made the backdoor design problem itself intractable to the attacker. They have scrambled the inputs that are supplied to hardware units at runtime, making it infeasible for malicious components to acquire the information they need to perform malicious actions.…”

“…Beaumont et al [11] have developed SAFER PATH architecture, which uses instruction, data fragmentation, program replication, and voting to create the computational system that is able to operate safely in the presence of active hardware Trojans. However, both of these works [10,11] lead to systems with considerable area and performance overheads.…”

SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware

“…Waksman and Sethumadhavan [7] propose bus scrambling, homomorphic cryptography, and time-guards. Bloom et al [10] use a double memory guard to securely pass encrypted data to and from memory.…”

“…Most research has focused on preventing the modification of an Integrated Circuit (IC), or methods for detecting a Hardware Trojan once it has been inserted into an IC. However, there can be no guarantee that an IC is free of Hardware Trojans before it is deployed [5], nor, given the large state-space of trigger mechanisms [6] is it possible to reliably prevent the activation of a Hardware Trojan in a device, despite current best efforts [7] [8].…”