Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

Moselund, Kirsten E.; Björk, Mikael; Schmid, Heinz; Ghoneim, H.; Karg, Siegfried; Lörtscher, Emanuel; Rieß, W.; Riel, Heike

doi:10.1109/ted.2011.2159797

Cited by 52 publications

(29 citation statements)

References 21 publications

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“…The ON current is around 0:02 lA=lm at V GS ¼ À4 V and V DS ¼ À0:5 V. We observe also that all the transfer characteristics show an average subthreshold swing ðSS avg Þ near 320 mV/dec, which is larger than 60 mV/decade. These results are relatively close to those presented in references [11][12][13]. In fact, Vallett et al have shown that using 5 nm of SiO 2 and 20 nm of HfO 2 as a gate stack oxide, they have obtained an I on current around 20 nA with a SS of about 370 mV/dec for V DS ¼ À0:5 V and V GS ¼ À12 V [13].…”

Section: Electrical Characterization At Roomsupporting

confidence: 89%

“…In order to optimize the electrical performance of the TFET (I on current, I on =I off ratio, SS...), it is necessary to control the abruptness of the tunnel junction, the doping level of the source/drain contact and the interface traps close to tunnelling junction. Lot of attention has been devoted to the fabrication of tunnel FET devices using nanowires fabricated by top-down and bottom-up approaches [7][8][9][10][11][12][13], in order to obtain a good electrical performance.…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, when the nanowires are grown vertically, it is possible to fabricate vertical transistors and so increase the 3D integration density and the ON current [15,16]. In the last years, few studies have shown the integration and the electrical characterization of p-i-n axially doped Si nanowires, elaborated by CVD-VLS method, on TFET devices [11][12][13]. In this context, we present the fabrication and the electrical properties as a function of temperature and in particular at high temperature of a single p-i-n SiNW gated diode.…”

Section: Introductionmentioning

confidence: 99%

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Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET

et al. 2015

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International audienceIn this paper, we present the fabrication and electrical characterization of a MOS gated diode based on axially doped silicon nanowire (NW) p-i-n junctions. These nanowires are grown by chemical vapour deposition (CVD) using the vapour-liquid-solid (VLS) mechanism. NWs have a length of about with of doped regions (p-type and n-type) and of intrinsic region. The gate stack is composed of 15 nm of hafnium dioxide (), 80 nm of nickel and 120 nm of aluminium. At room temperature, , and an ratio of about with a very low current has been obtained. Electrical measurements are carried out between 90 and 390 K, and we show that the I (on) current is less temperature dependent below 250 K. We also observe that the ON current is increasing between 250 and 390 K. These transfer characteristics at low and high temperature confirm the tunnelling transport mechanisms in our devices

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Section: Electrical Characterization At Roomsupporting

confidence: 89%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET

et al. 2015

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“…The tunnel FET has been identified as a promising candidate for low-power electronics as it can overcome the MOS limitations coming from the non-scalability of the inverse subthreshold slope (SS) [Chang et al 2010]. As demonstrated in Moselund et al [2011], nanowires are ideal to achieve a good tunnel FET as it requires the highest degree of electrostatic control. In particular, the key parameters to achieve good performance are the tunnel junction abruptness, the effective band gap at the tunneling junction, gate control over the channel, and overall device geometry.…”

Section: Low-power High-performances Devices: Towards Thin Devicesmentioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

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“…Its working principle is based on the band-to-band tunnelling of carriers. This is made possible by proper band engineering, achieved in top-gated FET operated in reverse bias, with p-i-n þ [74,129] or p-n-n þ [130] channel doping ( Fig. 7(b)).…”

Section: Steep-ss Nanowire Devicesmentioning

confidence: 99%