Silicon-on-insulator: materials aspects and applications

Plößl, A.; Kräuter, Gertrud

doi:10.1016/s0038-1101(99)00273-7

Cited by 59 publications

(30 citation statements)

References 18 publications

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“…However, a large range of values may be obtained, depending on the kind of SiC polytypes or surface terminations. 27 From the theoretical point of view, no value is available. Possible explanation is either the large size of the system that has to be dealt with first-principles methods or the difficulty to extract such energy from a slab calculation.…”

Section: Interface Energymentioning

confidence: 99%

Theoretical investigations of a highly mismatched interface: SiC/Si(001)

2003

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Using first principles, classical potentials, and elasticity theory, we investigated the structure of a semiconductor/semiconductor interface with a high lattice mismatch, SiC/Si͑001͒. Among several tested possible configurations, a heterostructure with ͑i͒ a misfit dislocation network pinned at the interface and ͑ii͒ reconstructed dislocation cores with a carbon substoichiometry is found to be the most stable one. The importance of the slab approximation in first-principles calculations is discussed and estimated by combining classical potential techniques and elasticity theory. For the most stable configuration, an estimate of the interface energy is given. Finally, the electronic structure is investigated and discussed in relation with the dislocation array structure. Interface states, localized in the heterostructure gap and located on dislocation cores, are identified.

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Section: Interface Energymentioning

confidence: 99%

Theoretical investigations of a highly mismatched interface: SiC/Si(001)

2003

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“…[1][2][3][4][5] During the past decade, direct wafer bonding has become an enabling technology responsible for a variety of state-of-the-art photonic devices, such as visible light emitting diodes ͑LED's͒ ͑including GaN-based ultraviolet/blue LEDs͒, 6,7 1.3 and 1.55 m edge emitting and vertical-cavity-surface-emitting lasers, 2-5,8 -10 high-speed resonant-cavity photodetectors, 11 etc. In addition, direct wafer bonding offers a solution to changing the relationship of crystallographic axes between integrated wafer pairs without forming device-degrading threading dislocations, providing an approach to creating layer structures that cannot be fabricated by epitaxial growth.…”

Section: Introductionmentioning

confidence: 99%

Hybrid-integrated GaAs/GaAs and InP/GaAs semiconductors through wafer bonding technology: Interface adhesion and mechanical strength

Shi

MacLaren

et al. 2003

Journal of Applied Physics

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In this study, the interface adhesion and mechanical strength of wafer bonded GaAs/GaAs and GaAs/InP semiconductors, each of (100) face, were characterized by combining the measurements of interface fracture energy γo and lap shear strength Es. The relations between the interface adhesion and annealing processes for four different types of bonding configurations, i.e., antiphase bonding, in-phase bonding, and twist bonding with 5° and 30° misalignments, were systematically studied. The surface free energy γα-GaAs/oxide (0.11–0.28 J/m2) of amorphous α-GaAs/oxide mixture was estimated based upon the reported surface free energy γc-GaAs (0.63 J/m2) of crystalline [100] GaAs and measured overall interface fracture energy γtotal (0.525 J/m2) of GaAs/GaAs bonded wafers. The micromorphologies of the bonded and debonded wafer interfaces were characterized by atomic force microscopy (AFM) and transmission electron microcopy (TEM). The interface microfailure mechanism of directly bonded GaAs wafers was proposed based on AFM and TEM microstructural analysis.

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“…if direct bonding is involved in subsequent processing steps. 14,15 In this paper, the topography of the oxide mask is investigated as a function of processing parameters through simulations, measurements, and analytical considerations. The study considers a fixed initial oxide mask thickness of 357 nm, in which mask windows are opened using either reactive ion etching or hydrofluoric acid.…”

mentioning

confidence: 99%

Thermal Oxidation of Structured Silicon Dioxide

Christiansen¹,

Hansen²,

Jensen³

et al. 2014

ECS J. Solid State Sci. Technol.

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The topography of thermally oxidized, structured silicon dioxide is investigated through simulations, atomic force microscopy, and a proposed analytical model. A 357 nm thick oxide is structured by removing regions of the oxide in a masked etch with either reactive ion etching or hydrofluoric acid. Subsequent thermal oxidation is performed in both dry and wet ambients in the temperature range 950°C to 1100°C growing a 205 ± 12 nm thick oxide in the etched mask windows. Lifting of the original oxide near the edge of the mask in the range 6 nm to 37 nm is seen with increased lifting for increasing processing temperatures. Oxides structured by reactive ion etching are lifted on average a factor of four more than oxides etched in hydrofluoric acid. Both simulations and the analytical model successfully predict the oxide topography qualitatively, showing that the mask lifting phenomenon is governed mainly by diffusion and the geometry of the oxide. Simulations also predict the oxide topography quantitatively, with an average root mean square deviation of 1.2 nm and a maximum deviation of 13 nm (39%) from the mean of the measured values.

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Silicon-on-insulator: materials aspects and applications

Cited by 59 publications

References 18 publications

Theoretical investigations of a highly mismatched interface: SiC/Si(001)

Theoretical investigations of a highly mismatched interface: SiC/Si(001)

Hybrid-integrated GaAs/GaAs and InP/GaAs semiconductors through wafer bonding technology: Interface adhesion and mechanical strength

Thermal Oxidation of Structured Silicon Dioxide

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