Silicon oxidation and Si–SiO<sub>2</sub> interface of thin oxides

Ravindra, Nuggehalli M.; Narayan, J.; Fathy, D.; Srivastava, J. K.; Irene, E. A.

doi:10.1557/jmr.1987.0216

Cited by 42 publications

(7 citation statements)

References 6 publications

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“…The most commonly used optical techniques are single wavelength and spectroscopic ellipsometry, 29,[70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85] reflectance difference spectroscopy ͑RDS͒, [86][87][88] second harmonic generation ͑SHG͒, [89][90][91][92][93][94][95][96][97] and Fourier transform infrared spectroscopy ͑FTIR͒. 82,98 -107 Ellipsometry is based on the measurement and subsequent modeling of changes in the polarization state of a light beam reflected from a sample surface, as is illustrated in Fig.…”

Section: A Optical Methodsmentioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

749

345

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The outstanding properties of SiO 2 , which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO 2 interface, which forms the heart of the modern metal-oxide-semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin ͑Ͻ4 nm͒ SiO 2 and Si-ON ͑silicon oxynitride͒ gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices will be manufactured with SiO 2 and Si-ON for the foreseeable future, continued scaling of integrated circuit devices, essentially the continued adherence to Moore's law, will necessitate the introduction of an alternate gate dielectric once the SiO 2 gate dielectric thickness approaches ϳ1.2 nm. It is hoped that this article will prove useful to members of the silicon microelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields, and graduate students. Parts of this article have been adapted from earlier articles by the authors ͓L.

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Section: A Optical Methodsmentioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

749

345

View full text Add to dashboard Cite

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“…A number of investigators [2][3][4] have reported that ellipsometry tends to overpredict SiO 2 film thicknesses for thicknesses much less than 100 Å. To test this assertion, the oxide was chemically removed from a portion of the substrate on several specimens and atomic force microscopy (AFM) used to directly measure the thickness of the resulting oxide step.…”

Section: Methodsmentioning

confidence: 99%

Planar oxidation of strained silicon substrates

2001

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We report here on a series of experiments in which relatively low levels of in-plane bending strain were applied to oxidizing silicon substrates. These were found to result in significant decreases in oxide thickness in the ultrathin oxide regime. Both tensile and compressive bending resulted in roughly the same degree of thickness retardation, although compressive bending typically led to somewhat thinner oxides than did tensile bending. An examination of the experimental data indicate that the principal effect seems to occur in the very early stages of oxidation, with only minor effects on subsequent oxide growth. We hypothesize that the observed oxide thickness retardation is related to straining of the underlying silicon lattice at the oxidation front.Here h is the specimen thickness, M the bending moment felt by the specimen, and I the area moment of inertia of

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“…Understanding the growth of oxide on Si has been one of the major issues of microelectronics from the dawn of the technology. The kinetics of oxide growth has been studied by E. Irene et al , already in the late 1970s using real-time SE, followed by several other studies of the same group, − also for silicides . The real-time measurement of the oxidation of Si has also been demonstrated in a vertical furnace that has a smaller-sized system along with better contamination control. , Laser-induced oxidation has been investigated by A.V.…”

Section: Investigation Of Processesmentioning

confidence: 99%

Real-Time Ellipsometry at High and Low Temperatures

Mukherjee

Petrik

2023

ACS Omega

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Among the many available real-time characterization methods, ellipsometry stands out with the combination of high sensitivity and high speed as well as nondestructive, spectroscopic, and complex modeling capabilities. The thicknesses of thin films such as the complex dielectric function can be determined simultaneously with precisions down to sub-nanometer and 10–4, respectively. Consequently, the first applications of high- and low-temperature real-time ellipsometry have been related to the monitoring of layer growth and the determination of optical properties of metals, semiconductors, and superconductors, dating back to the late 1960s. Ellipsometry has been ever since a steady alternative of nonpolarimetric spectroscopies in applications where quantitative information (e.g., thickness, crystallinity, porosity, band gap, absorption) is to be determined in complex layered structures. In this article the main applications and fields of research are reviewed.

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Silicon oxidation and Si–SiO₂ interface of thin oxides

Cited by 42 publications

References 6 publications

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Planar oxidation of strained silicon substrates

Real-Time Ellipsometry at High and Low Temperatures

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Silicon oxidation and Si–SiO2 interface of thin oxides

Cited by 42 publications

References 6 publications

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Planar oxidation of strained silicon substrates

Real-Time Ellipsometry at High and Low Temperatures

Contact Info

Product

Resources

About

Silicon oxidation and Si–SiO₂ interface of thin oxides

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits