Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging

Kopp, Christophe; Bernabé, Stéphane; Bakir, Badhise Ben; Fédéli, Jean-Marc; Orobtchouk, Régis; Schrank, Franz; Porte, H.; Zimmermann, Lars; Tekin, Tolga

doi:10.1109/jstqe.2010.2071855

Cited by 229 publications

(109 citation statements)

References 29 publications

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“…Semiconductor heterostructures comprising GeSn alloys are more and more considered a serious candidate as active material for light emitting devices integrated into the Si-CMOS technology 1 after the demonstration of lasing using this material system. [2][3][4] Nonetheless, in order to move toward real-market applications, several issues still have to be addressed such as the low laser operating temperature.…”

mentioning

confidence: 99%

The thermal stability of epitaxial GeSn layers

et al. 2018

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We report on the direct observation of lattice relaxation and Sn segregation of GeSn/Ge/Si heterostructures under annealing. We investigated strained and partially relaxed epi-layers with Sn content in the 5 at. %-12 at. % range. In relaxed samples, we observe a further strain relaxation followed by a sudden Sn segregation, resulting in the separation of a β-Sn phase. In pseudomorphic samples, a slower segregation process progressively leads to the accumulation of Sn at the surface only. The different behaviors are explained by the role of dislocations in the Sn diffusion process. The positive impact of annealing on optical emission is also discussed.

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mentioning

confidence: 99%

The thermal stability of epitaxial GeSn layers

et al. 2018

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“…Grating couplers have much a better alignment tolerance amounting to ±2.5 µm 1 dB power penalty and a CMOS compatible planar processing that is suitable for high volume manufacturing and wafer-scale testing. Commercial packaging service ePIXpack offers multiport fiber array connector of up to 32 ports [63][64][65]. The fibers are mounted vertically on a v-groove bottom with a glass lid that is polished at near normal coupling angle to the SOI chip, along with a glob-top encapsulation (see Figure 18a).…”

Section: Packaging and Testingmentioning

confidence: 99%

“…Two prominent fiber-chip packaging schemes. (a) Vertically mounted rigid fiber array coupling from g-pack, a packaging service offered by ePIXpack ( image reprinted with permission from [65]). (b) Multiarrayed fiber packaging with quasi-planar coupler at input and output ends of a photonic integrated circuit (Image courtesy of Tyndall National Institute).…”

Section: Packaging and Testingmentioning

confidence: 99%

Grating-Assisted Fiber to Chip Coupling for SOI Photonic Circuits

2018

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Fiber to chip coupling is a critical aspect of any integrated photonic circuit. In terms of ease of fabrication as well as wafer-scale testability, surface grating couplers are by far the most preferred scheme of the coupling to integrated circuits. In the past decade, considerable effort has been made for designing efficient grating couplers on Silicon-on-Insulator (SOI) and other allied photonic platforms. Highly efficient grating couplers with sub-dB coupling performance have now been demonstrated. In this article, we review the recent advances made to develop grating coupler designs for a variety of applications on SOI platform. We begin with a basic overview of design methodology involving both shallow etched gratings and the emerging field of subwavelength gratings. The feasibility of reducing footprint by way of incorporating compact tapers is also explored. We also discuss novel grating designs like polarization diversity as well as dual band couplers. Lastly, a brief description of various packaging and wafer-scale testing schemes available for fiber-chip couplers is elaborated.

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“…The grooves could be a V-shape trench prepared by Si wet etching or a rectangular trench realized by Si deep reactive ion etching (RIE) [59]. In another study, low-cost devices like datacom modules have been fabricated using similar MEMS technologies [60].…”

Section: Optical Couplingmentioning

confidence: 99%

Low-Temperature Bonding for Silicon-Based Micro-Optical Systems

Howlader

Deen

2015

Photonics

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Abstract:Silicon-based integrated systems are actively pursued for sensing and imaging applications. A major challenge to realize highly sensitive systems is the integration of electronic, optical, mechanical and fluidic, all on a common platform. Further, the interface quality between the tiny optoelectronic structures and the substrate for alignment and coupling of the signals significantly impacts the system's performance. These systems also have to be low-cost, densely integrated and compatible with current and future mainstream technologies for electronic-photonic integration. To address these issues, proper selection of the fabrication, integration and assembly technologies is needed. In this paper, wafer level bonding with advanced features such as surface activation and passive alignment for vertical electrical interconnections are identified as candidate technologies to integrate different electronics, optical and photonic components. Surface activated bonding, superior to other assembly methods, enables low-temperature nanoscaled component integration with high alignment accuracy, low electrical loss and high transparency of the interface. These features are preferred for the hybrid integration of silicon-based micro-opto-electronic systems. In future, new materials and assembly technologies may emerge to enhance the performance of these micro systems and reduce their cost. The article is a detailed review of bonding techniques for electronic, optical and photonic components in silicon-based systems.

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Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging

Cited by 229 publications

References 29 publications

The thermal stability of epitaxial GeSn layers

The thermal stability of epitaxial GeSn layers

Grating-Assisted Fiber to Chip Coupling for SOI Photonic Circuits

Low-Temperature Bonding for Silicon-Based Micro-Optical Systems

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