Silicon photonics research for CMOS compatible optical interconnects at 40Gb/s and beyond

Bœuf, F.; Fulbert, L.; Baudot, Charles; Fédéli, Jean-Marc; Vivien, Laurent; Bakir, Badhise Ben; Virot, L.; Caire-Remonnay, Boris; Liepvre, A. Le; Kopp, Christophe; Grosse, Philippe; Bernabé, Stéphane; Menezo, Sylvie

doi:10.1109/iscdg.2012.6359986

Cited by 2 publications

(1 citation statement)

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“…To this end, multiplexing (MUX)/demultiplexing (DEMUX) structures featuring low-cost integration, compactness, high throughput (via the number of channels and their pass band bandwidths), low crosstalk and low power consumption appear as an essential building block toward the implementation of high-performance on-chip optical interconnects. In this perspective, silicon photonics, as a well-matured, CMOS-compatible, cost-effective and chip-level interconnect technology platform, holds the credentials to meet these requirements [17]- [20].…”

Section: Introductionmentioning

confidence: 99%

On-Chip Dual-Stream DWDM Eight-Channel-Capable SOI-Based MUX <roman>s</roman>/DEMUX <roman>s</roman> With 40-GH <roman>z</roman> Channel Bandwidth

et al. 2015

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We demonstrate two 8 Â 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/ demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being $12 and $9 m, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 W/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than $18 dB crosstalk and higher than $40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 Â 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proofof-concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties.

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Section: Introductionmentioning

confidence: 99%