2016
DOI: 10.1007/s00542-016-2941-0
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Silicon tip sharpening based on thermal oxidation technology

Abstract: Silicon tips are conventionally fabricated by isotropic etching followed by oxidation sharpening at temperatures below 1050 °C, based on the reduced oxidation rate at the step edge due to high compressive stress around the edge (Marcus and Sheng 1982). However, the effects of the oxidation temperature on the tip profile have been far from studied yet. This work investigated in detail the optimized oxidation temperature to fabricate sharp tips with high aspect ratio. The results indicated that a trade-off betwe… Show more

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Cited by 16 publications
(14 citation statements)
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“…The mismatch of the volume gives SiO 2 compressive stress, which decreases the diffusion constant of oxygen. The stress at the Si/SiO 2 interface around the convex or concave corner is difficult to release, thus slows down the oxidation rate and leads to tip sharpening [39]. The glass transition temperature of SiO 2 is 960 • C [40].…”
Section: Resultsmentioning
confidence: 99%
“…The mismatch of the volume gives SiO 2 compressive stress, which decreases the diffusion constant of oxygen. The stress at the Si/SiO 2 interface around the convex or concave corner is difficult to release, thus slows down the oxidation rate and leads to tip sharpening [39]. The glass transition temperature of SiO 2 is 960 • C [40].…”
Section: Resultsmentioning
confidence: 99%
“…Besides, thermal oxidation of Si at low-temperature for tip sharpening is limited by the oxide thickness, usually less than 500 nm, thus the neck width should be less than 500 nm [ 41 ]. Therefore, precisely controlling the isotropic etching rate and time is critical for realizing a desired neck width within a tolerance as small as tens of nanometers.…”
Section: Resultsmentioning
confidence: 99%
“…Figure 1 described the fabrication process of a nanotip based on isotropic ICP etching, including patterning the photoresist, isotropic etching of silicon, tip sharpening by oxidation [ 41 ], and tip releasing. A 4-inch (100)-oriented Si wafer was used (IceMOS, Hannahstown, Belfast, UK).…”
Section: Fabrication Processmentioning
confidence: 99%
“…[8,13] Each of these additional fabrication steps requires expensive equipment and adds practical difficulties directly affecting the tip's quality. [14] To overcome these issues, Liu et al fabricated self-sharpened Si tips without the oxidative sharpening step by using a square pattern aligned at a specific angle to the (110) orientation. The critical etch condition (Equation ( 1)) for self-sharpened tips was expressed in terms of critical anisotropy ratio 𝜂 c [15]…”
Section: Introductionmentioning
confidence: 99%