Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface

Abstract

Power integrity has become increasingly important for the designs in 32 nm or below. This paper discusses a siliconvalidated methodology for power delivery (PD) modeling and simulation. Many prior works have focused on PD analysis and optimization. However, none of them provided a comprehensive modeling methodology with postsilicon data to validate the use of the models. In this paper, we present PD system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32-nm industrial double date-rate I/O design. Our models are able to capture the unique impacts of on-die inductance, state-dependent coupling capacitance, and diepackage interaction. Those impacts are prominent for the designs in 32 nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for PD analysis.

Worst-Case Dynamic Power Distribution Network Noise Prediction Using Convolutional Neural Network

“…With the continuous voltage scaling and ever growing integration density, power supply noise has become a concerning issue in modern lower power SoC designs [1][2][3][4]. A too large supply noise of the power distribution network (PDN) for an SoC not only degrades the performance of critical circuits, but also impairs its reliability [1].…”

“…A too large supply noise of the power distribution network (PDN) for an SoC not only degrades the performance of critical circuits, but also impairs its reliability [1]. Thus, the worst-case supply noise validation has become an essential step in power delivery sign-off [2].…”

“…1 shows an illustrative plot of on-die power grid, which may contain more than ten metal layers with wire pitches up to several nano-meter for advanced technologies [1,2]. Since the worst-case noise validation (WNV) needs to be accurate for signoff, in commercial practices, WNV is commonly conducted with very detailed distributed RC/RLC model representing the on-die grid along with package and board modelled as macro-models [2]. Obviously, such a simulation needs to solve the voltages for millions to billions of nodes in the on-die grid, which is a non-trivial problem.…”

“…. $15.00 https://doi.org/10.1145/3489517.3530600 It has been reported that, for 32nm commercial memory controller, even the commercial tool takes up to 24 hours to solve a few hundred nano-second trace when accounting for the entire PDN from board to die [2]. On the other hand, since there are many application scenarios for an SoC, WNV needs to be executed for tens of test vectors during sign-off, which makes it very time-and resourceconsuming [3].…”