Similarities and Differences of BTI in SiC and Si Power MOSFETs

Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs

“…14 show that the threshold voltage shift is directly proportional to the stress voltage and it is more apparent for the negative gate stresses, as expected for N-channel MOSFETs [60]. The higher impact of NBTI has been reported in [61,62], with improvements in NBTI performance if the manufacturing process is optimized [47,62]. Studies in [16] reported a high concentration of traps with small capture/emission times for NBTI compared with PBTI, but further studies are required to identify the physical nature of the defects causing the BTI-induced VTH shifts [16,21].…”

“…As stated previously, the gate oxide reliability of SiC MOSFETs has been one of the main fabrication issues [13]. The higher defect density in the SiO2/SiC interface [13,17] together with the reduced band offsets to the dielectric [17,47] make the gate dielectric interface and BTI in SiC MOSFET more complex. The mechanisms of BTI in SiC MOSFETs [16] are the same as in silicon devices.…”

Measurement and simulation of short circuit current sharing under parallel connection: SiC MOSFETs and SiC Cascode JFETs

“…Furthermore, even when VTH variability is reduced when designing power modules by selecting devices with the same VTH, variation in VTH drift [13] over the lifetime of the module can become a problem. VTH drift due to BTI is a challenge in SiC MOSFETs, whereas SiC Cascode JFETs do not have this problem since the input device is a low voltage silicon MOSFET and the VTH in silicon MOSFETs is stable with low variability [14].…”

Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

“…At the same time, these circuits should also extract the parameters of interest (e.g., V TH and R ON ) without affecting device operation. Accordingly, a fast stress measurement approach is needed, in order to cope with switching frequencies in the kHz range [11] and also to limit the delay between the stress and readout [12][13][14] phases, thus avoiding ambiguous parameter drifts and/or wrong data interpretation. Nevertheless, achieving these goals is challenging for conventional parameter analyzers, especially when characterizing packaged devices with large parasitic capacitances [15].…”