Simple and controlled single electron transistor based on doping modulation in silicon nanowires

Abstract

A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and therefore controlled by lithography. The source and drain capacitances have also been characterized. This design could be used to build more complex SET devices.The first and most common Coulomb blockade device is the Single Electron Transistor (SET) made with metallic leads and island, and tunnel oxide barriers 1,2 . It is used as sensitive electrometers 3 or electron pumps allowing to control the transfer of electrons one by one 4,5 . Since then very important efforts have been devoted to fabricate silicon SETs, mostly to integrate SETs together with regular transistors for building logic circuits 6,7 , and more recently for quantum logic experiments with single charge or spin in silicon quantum dots 8,9 . An important challenge is to increase the temperature of operation from the typical sub-kelvin range of original devices up to much higher temperatures. The required size of the island is of the order of the nm, and therefore out of control of current fabrication processes. Researchers took advantage of natural disorder to create such extremely small islands, mostly with constrictions in disordered thin films 10,11,12,13,14 . More recently 15 undulated thin films have been used, as well as pattern-dependent oxidation 16 .We followed another approach based on etched silicon nanowires without constrictions, as pionnered by Tilke et al. 17 and more recently Namatsu et al. 18 , and also Kim et al. 19 and Fujiwara et al. 20 . In the two first cases the formation of a Coulomb island in a nanowire underneath a very large gate was studied. In the two others two gates were defined above a nanowire, each of them acting as a tunable barrier for entering/exiting the single electron box delimited by these gates. Although this scheme allowed logic operations to be performed at 300K 15,16 , it remains a complex architecture since up to 4 gates are needed for proper operation. Our SET is much simpler since it requires a single gate to define the quantum dot, while the barriers are fixed, like in metallic SETs. Periodic Coulomb blockade is observed, with a period solely determined by the surface area of a single gate. It is therefore controlled by lithography, not by disorder. With current state of the art electron beam lithography the limit in operating temperature is of the order of 10 K. The schematics of our device is essentially similar to the original metallic SETs, the tunnel oxide barriers being re-

Few electron limit of n-type metal oxide semiconductor single electron transistors

“…Moreover we notice that there is no significant shift between the threshold voltage obtained at T =300 K (∼ -40 mV calculated as the maximum of the second derivative of the drain current with respect to the gate voltage, see inset of Figure 2b) and the gate voltage position of the first Coulomb peak at low temperature (V g = 40 mV), taking into account the thermal broadening at T =300 K. The presented samples are smaller than similar samples previously studied (L,W =30-40 nm, [10] and [17]). The silicon thickness (T Si =10 nm) and the spacer length (11 nm) have been scaled down accordingly to obtain a good trade-off between the first electron orbital-electrodes coupling and a large Coulomb energy.…”

“…the transistor's channel is separated from the source and drain by the small low-doped region below the spacers. This non-overlapped geometry is responsible for the SET behavior [10]. Figure 1a shows a transmission electron micrograph of a tri-sided gate nanowire MOSSET coming from a wafer used for the morphological characterization with channel thickness T Si =17 nm, oxide thickness T ox =4 nm and gate length L g =22 nm realized with a process identical to the samples reported throughout the text.…”

“…Indeed barriers are consequence of undoped silicon below spacers which are on both sides of the gate. [10] In the past, this approach has been exploited to fabricate compact double and triple quantum dots realized with only two gates. [11] The two main advantages are on one hand its compactness, as regard to state-of-the-art previous works on Si including additional upper gate [12], and on the other one the detection of a clear single electron regime.…”

Ultrasmall silicon quantum dots

“…The corresponding potential fluctuations can result in localization on short length scales, and thus multiple dots connected in series. Nearly all reports so far have been on Si quantum dots greater than 50 nm, e.g., in Si metal oxide semiconductor field effect transistors, [4][5][6] silicon-on-insulator structures, [1][2][3]7 and Si/SiGe heterostructures. 8,9 In these three systems excited states have been observed only recently.…”

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

“…This is followed by the undoped, square Si (001) channel of thickness 12 nm, which is achieved by etching down the SOI substrate prior to gate stack deposition. Each top-gate wraps around two faces of the intrinsic channel and is separated from the other top-gates by the Si 3 N 4 spacers and from the channel by 5 nm of SiO 2 [15]. A quantum dot can be created under each gate at the top-most corners of the channel due to the so-called corner effect [10,11,16].…”