Simple scheme to increase hold voltage for silicon‐controlled rectifier

Hung, Chung-Yu; Kao, Tzu-Cheng; Lee, Jian–Hsing; Gong, Jeng; Huang, Tsung–Yi; Su, Hung-Der; Chang, Kuo-Cheng; Huang, Chun‐Wei; Lo, Kuo-Hsuan

doi:10.1049/el.2013.1853

Cited by 10 publications

(2 citation statements)

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“…Several reports demonstrated that the holding voltage of SCR is mainly determined by the potential difference across the NWELL/PWELL depletion region V dep [18][19][20], which is inversely proportional to the minority carriers (electrons/holes) injected into the depletion region. While the branch path of EP-LVTSCR can extract holes/ electrons injected into the depletion region from the SCR path, thus elevating the V h of EP-LVTSCR.…”

Section: Methodsmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

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Section: Methodsmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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“…Further Evidence of this phenomenon can be demonstrated by the potential difference around the trigger point and after the holding point, as shown in figures 10(a) and (b). Upon conduction, the voltage V Aon across the device can be given by [25]…”

Section: Two-dimensional Simulation Of Scrmentioning

confidence: 99%

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

Liu,

Wang,

Yang

et al. 2024

Semicond. Sci. Technol.

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The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic PNP transistors for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1), a 96.1% improvement in holding voltage (Vh), and achieves an equivalent Human Body Model (HBM) protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

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