Simplified Design of Constant Coefficient Multipliers

Abstract

In many digital signal processing algorithms, e.g., linear transforms and digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work two approaches to realize constant coefficient multiplication with few adders and subtracters are presented. The first yields optimal results, i.e., a minimum number of adders and subtracters, but requires an exhaustive search. Compared with previous optimal approaches, redundancies in the exhaustive search cause the search time to be drastically decreased. The second is a heuristic approach based on signed-digit representation and subexpression sharing. The results for the heuristic are worse in only approximately 1% of all coefficients up to 19 bits. However, the optimal approach results in several different optimal realizations, from which it is possible to pick the best one based on other criteria. Relations between the number of adders, possible coefficients, and number of cascaded adders are presented, as well as exact equations for the number of required full and half adder cells. The results show that the number of adders and subtracters decreases on average 25% for 19-bit coefficients compared with the canonic signed-digit representation.

Alternatives for low-complexity complex rotators

“…For the cases of scaled constant multiplication (SCM) the coefficient indicates how the constant value cos α/ sin α is quantized. The hardware architecture that uses the indicated number of adders can be obtained from these values [10].…”

“…Adders and substractors have same complexity so we refer to both as adders. When an input signal is multiplied by more than one constant, a simple method is to realize each multiplier individually, which can be done optimally for up to 19-bits coefficients [10]. However, it is also possible to utilize redundancies between the constants in order to reduce the complexity of the hardware.…”

“…In the case under study, this scaling can be incorporated to the corresponding constant of the quantizer, leading to savings in the number of adders. The resulting constant multiplications can be straightforwardly realized using the optimal approach in [10]. The analogous case consist in taking the common factor cos α according to:…”

Low-complexity rotators for the FFT using base-3 signed stages

“…This gives 2 + 2 · MCM(C i , S i ) adders, where MCM(C i , S i ) is the number of adders needed for a multiplication by C i and S i simultaneously. In the case when δ i = 0, only a single constant multiplication (SCM) [13] is used, and applied on x i and y i , giving 2 · SCM(K i ) adders, where SCM(K i ) is the number of adders needed for the multiplication by K i .…”

4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

“…. The constant multiplier can be realized using a minimum number of adders using the method in [14].…”