Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud

Abstract

The design of high-performance Multiprocessor Systems-on-Chip (MPSoCs) has proven to be an attractive challenge in embedded systems design automation. However, the complexity of such designs associated with short timeto-market constraints impose serious limitations on the exploration of different configurations and scenarios on the design space exploration. The use of virtual platforms may decrease the time-to-market of these architectures while providing the means to exploit, debug and verify architectures with different features. In this paper, we present the webbased Simplify framework, an interactive approach for MPSoC exploration using an instruction-accurate Open Virtual Platform (OVP). The framework provides an environment to define both software and hardware properties in an intuitive way, and allows designers to validate the functionality as well as the behavior of the modeled architectures at highabstraction levels. Based on the simulation reports generated from the framework, designers can perform further design modifications and optimizations, and re-validate the whole system in an efficient way, allowing increased design space exploration. For the evaluation of the proposed approach, a set of benchmark applications extracted from MiBench has been used. They run on five different processors (MIPS32, ARM7, OpenRISC (OR1K), PowerPC32 and MicroBlaze) on both mono and multiprocessor architectures and the experiments show considerable simulation speed-ups to obtain application profiling at instruction-level compared to existing approaches based on tracing.

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

“…A platform is modelled through the following sets of APIs: The use of OVP to model heterogeneous multiprocessor architectures is described in [17] through a set of case studies. A drag and drop interactive approach for MPSoC exploration using OVP is proposed in [18]. A technique exploiting OVP for development and optimization of embedded computing applications by handling heterogeneity at the chip, node, and network level is proposed in [19].…”

“…At platform level, a signal is used to connect the virtual device to the interrupt lines provided by the platform chipset (line 36). When an interrupt is generated by the SystemC device, the interrupt is notified to the chipset through such a signal (lines [18][19]. To catch the interrupt from the SystemC module, the virtual device creates an OVP thread (line 40-41) that cyclically checks the is_ready line of the SystemC module (lines 1-21).…”

Parallelization of genetic algorithms for sorting permutations by reversals over biological data

“…Authors in [3] have observed that applications running on different processors have significant differences in performance. Therefore, chosen an appropriate processor, or a set of them, to execute the GA might be very Besides that, the OVP uses cross-compilers directly coupled with the target processor, which makes it possible that applications previously compiled to OVP can easily run on hardware architectures without the need of porting the code.…”

A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms

“…The use of OVP to model heterogeneous multiprocessor architectures is described in [13] through a set of case studies. A drag and drop interactive approach for MPSoC exploration using OVP is proposed in [14]. A technique exploiting OVP for development and optimization of embedded computing applications by handling heterogeneity at the chip, node, and network level is proposed in [15].…”