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The rising use of RFID has been stimulating the world market through strong financial investments heading for the adoption of RFID as a standard identification technology. Such initiative has been fomenting the necessity of an infrastructure able to deal with the restrictions and limitations imposed by business areas and RFID environments. This work presents a modular and adaptive framework architecture that implements the EPC Network specifications and that aims at facilitating the RFID applications development. The framework is composed by modules that provide communication interfaces for different applications and reader devices and also a set of functions for data processing and information services. For the work validation, the framework was integrated in a real system for fuel supply control of vehicle fleets and the results demonstrated its efficiency in the integration of RFID systems.

The design of high-performance Multiprocessor Systems-on-Chip (MPSoCs) has proven to be an attractive challenge in embedded systems design automation. However, the complexity of such designs associated with short timeto-market constraints impose serious limitations on the exploration of different configurations and scenarios on the design space exploration. The use of virtual platforms may decrease the time-to-market of these architectures while providing the means to exploit, debug and verify architectures with different features. In this paper, we present the webbased Simplify framework, an interactive approach for MPSoC exploration using an instruction-accurate Open Virtual Platform (OVP). The framework provides an environment to define both software and hardware properties in an intuitive way, and allows designers to validate the functionality as well as the behavior of the modeled architectures at highabstraction levels. Based on the simulation reports generated from the framework, designers can perform further design modifications and optimizations, and re-validate the whole system in an efficient way, allowing increased design space exploration. For the evaluation of the proposed approach, a set of benchmark applications extracted from MiBench has been used. They run on five different processors (MIPS32, ARM7, OpenRISC (OR1K), PowerPC32 and MicroBlaze) on both mono and multiprocessor architectures and the experiments show considerable simulation speed-ups to obtain application profiling at instruction-level compared to existing approaches based on tracing.

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