Simplifying FPGA Implementations of BLAKE Hash Algorithm with Block Memory Resources

Sugier, Jarosław

doi:10.1016/j.proeng.2017.01.057

Cited by 7 publications

(6 citation statements)

References 5 publications

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“…Hardware design [21], [23], [24], [25], [26], [27] authors can maintain the high throughput while offering the robustness and reliability but usually involve the highest cost. The application specific and modular hardware design [28], [29], [31] can achieves extraordinary power and offers high reliability but comes with higher cost due to the need of additional hardware and lost speed of operation.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Lakshmi¹

2020

IJATCSE

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Now a day all the communications are carried out in wireless medium. It is necessary to transmit the confidential data in wireless media in secure manner. Cryptography is technique to protect electronic data in communication network. Hardware implementation of cryptography processor in field programmable gate array (FPGA) is major issues in terms of area, power and throughput. In this paper, we propose a hybrid crypto processor (HCP) for wireless network using flexible encryption and signature techniques. The main aim of proposed HCP technique used to provides secure wireless communication with aware of malicious attacks in the network, know to my knowledge, the proposed HCP hardware design is open the platform in signcryption. Generally, hybrid cryptography consists of data encapsulation mechanism (DEM) and key encapsulation mechanism (KEM). In HCP design, the efficient multiplier based ECC processor is proposed for data encapsulation over Galois field (GF (2 m )). Moreover, the improved enhanced Kurosawa and Desmedt hashing (EKD) hashing scheme is proposed for key encapsulation. The proposed HCP design is implementing in Xilinx tool with different field programmable gate array (FPGA) families. The result shows that effectiveness of proposed HCP design in terms of hardware utilization, power consumption and throughput over existing design.

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Section: Related Workmentioning

confidence: 99%

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Lakshmi¹

2020

IJATCSE

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“…After encryption, the plain text converts into the Cipher Text (CT). With the help of key, the cipher text has is converted to original data [15].…”

Section: Crypt-analytics Mechanismmentioning

confidence: 99%

“…• BP function has (12+2x1) iterations of 5 sub rounds (f = l, α, β, µ, ʎ) o l: one word is created by XOR round constant o α: Bitwise rows o β: permute the 25 words o µ: bitwise rotation o ʎ: XOR with two 5xw columns neighbors.…”

Section: Block Permutation (Bp)mentioning

confidence: 99%

“…Methodology Advantage Disadvantage Performance Measure Jaroshaw Sugier [15] FPGA implementation of BLAKE hash algorithm with black memory resources. This block algorithm was developed for SHA-3.…”

Section: Authormentioning

confidence: 99%

“…High dimensional binary codes consider as a hash function which has high efficiency [2]. The SHA algorithm has been published in the National Institute of Standard Technology (NIST) [3][4].The Black algorithm based hash function used for secure the data which maps with binary data [5]. For security, Advanced Encryption Standard (AES) based algorithms used in many research papers.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reconfigurable FPGA Architecture for Cryptographic Hashing Algorithms

2019

IJITEE

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Nowadays, security is the most significant thing in the communication field. Most of the data transmitted over the communication channel are highly confidential so it needs more security. But this confidential data are easily stolen by hackers and it affects the users’ privacy. Nowadays, so many encryption algorithms have been established to protect the original information of the users. But, Hash Function (HF) security is the most important primitive which used for data authentication and data integrity. The reconfigurable cryptography integrated with chip which used for cryptography. Hashing algorithm is used to generate the random number which also used as a key value for cryptography. In this paper, different kind of Secured Hash Algorithms (SHA) such as SHA-0, SHA-1, SHA-2, and SHA-3 in that the SHA-2 has different family (SHA-2F) such as SHA-224, SHA-256, SHA-384, and SHA-512 is studied.

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FPGA Implementations of BLAKE3 Compression Function with Intra-Round Pipelining

Sugier

2022

New Advances in Dependability of Networks and Systems

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Simplifying FPGA Implementations of BLAKE Hash Algorithm with Block Memory Resources

Cited by 7 publications

References 5 publications

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Reconfigurable FPGA Architecture for Cryptographic Hashing Algorithms

FPGA Implementations of BLAKE3 Compression Function with Intra-Round Pipelining

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