SimSoC: A SystemC TLM integrated ISS for full system simulation

Helmstetter, Claude; Joloboff, Vania

doi:10.1109/apccas.2008.4746381

Cited by 24 publications

(11 citation statements)

References 9 publications

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“…SystemC, along with a methodology based on Transaction Level Modeling (TLM), has been used in a number of works [15], [17]. This methodology is based on the classic Design-Implement-Redesign spiral model which is common in software development, and takes advantage of the wide range of simulation capabilities offered by SystemC: starting from a functional model (i.e., a C++ implementation of the algorithm), it is possible to iteratively add detail to different components of the system, creating more detailed models that approach the low-level RTL code necessary for actual implementation without losing confidence in the functionality of the code.…”

Section: B Methodologymentioning

confidence: 99%

Multiple-person tracking devoted to distributed multi smart camera networks

Zuriarrain

Aizpurua

Lerasle

et al. 2010

2010 IEEE/RSJ International Conference on Intelligent Robots and Systems

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Camera networks are an important component of modern complex systems, be it for surveillance, human/machine interaction or healthcare. Having smart cameras that can, by themselves, perform part of the data processing improves scalability both in processing and network resources. In this paper, we present the HYBRID algorithm for multiple person tracking intended for implementation on a smart camera platform, along with the development methodology to implement said algorithm in an FPGA-based smart camera. The HYBRID strategy outperforms the well-known Markov Chain Monte Carlo based particle filter (MCMC-PF) in terms of (i) parallelization capabilities as the MCMC-PF sequentially processes the particles, and (ii) tracking performances (i.e., robustness and precision).

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Section: B Methodologymentioning

confidence: 99%

Multiple-person tracking devoted to distributed multi smart camera networks

Zuriarrain

Aizpurua

Lerasle

et al. 2010

2010 IEEE/RSJ International Conference on Intelligent Robots and Systems

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“…The TCDM is partitioned into M banks, where all banks have the same memory capacity. For the ARMv6 processor models we use the Instruction Set Simulator in [6] wrapped in a SystemC module. A logarithmic interconnect supports communication between the processors and the TCDM banks.…”

Section: Target Architecturementioning

confidence: 99%

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures

Papagiannopoulou

Marongiu

Moreshet

et al. 2018

Int J Parallel Prog

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Hardware transactional memory exploration in coherence-free many-core architectures This work was made openly accessible by BU Faculty. Please share how this access benefits you. Your story matters.Abstract High-end embedded systems, like their general-purpose counterparts, are turning to many-core cluster-based shared-memory architectures that provide a shared memory abstraction subject to non-uniform memory access (NUMA) costs. In order to keep the cores and memory hierarchy simple, many-core embedded systems tend to employ simple, scratchpad-like memories, rather than hardware managed caches that require some form of cache coherence management. These "coherence-free" systems still require some means to synchronize memory accesses and guarantee memory consistency. Conventional lock-based approaches may be employed to accomplish the synchronization, but may lead to both usability and performance issues. Instead, speculative synchronization, such as hardware transactional memory, may be a more attractive approach. However, hardware speculative techniques traditionally rely on the underlying cache-coherence protocol to synchronize memory accesses among the cores. The lack of a cache-coherence protocol adds

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“…SimSoC [5] presents the design of an ARM based system. The framework integrates ISSs as SystemC modules with other platform components by means of TLM interfaces.…”

Section: Related Workmentioning

confidence: 99%

LEON3 ViP: A Virtual Platform with Fault Injection Capabilities

Silva¹,

Sánchez

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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In addition to functional simulation for validation of hardware/software designs, there are additional robustness requirements that need advanced simulation techniques and tools to analyze the system behavior in the presence of faults. In this paper, we present the design of a fault injection framework for LEON3, a 32bit SPARC CPU based system used by the European Space Agency, described at Transaction Level using SystemC. First of all an extension of a previous XML formalization of basic binary faults, like memory and CPU registers corruption, is done in order to support TLM2.0 transaction's parameters corruptions. Next a novel Dynamic Binary Instrumentation (DBI) technique for C++ binaries is used to insert fault injection wrappers in SystemC transaction path. For binary faults in model components the use of TLM2.0 "transport_dbg" is proposed. This way each component with fault injection capabilities exposes a standard interface to allow internal component inspection and modification.

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SimSoC: A SystemC TLM integrated ISS for full system simulation

Cited by 24 publications

References 9 publications

Multiple-person tracking devoted to distributed multi smart camera networks

Multiple-person tracking devoted to distributed multi smart camera networks

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures

LEON3 ViP: A Virtual Platform with Fault Injection Capabilities

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