Simulated Annealing Algorithm &amp; ReRAM Device Co-optimization for Computation-in-Memory

Taoka, Kenta; Misawa, Naoko; Koshino, Shunsuke; Matsui, Chihiro; Takeuchi, Ken

doi:10.1109/imw51353.2021.9439610

Cited by 12 publications

(14 citation statements)

References 2 publications

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“…23) However, NVM devices have non-ideal properties such as quantization error of memory device conductance, conductance variation, and wearing out by switching. [24][25][26][27][28][29] Figures 9(a) and 9(b) show the measured conductance variation of an ReRAM memory device 30,31) at Set/Reset 10 4 cycles and 10 6 Set/Reset cycles, respectively. ReRAM can switch between HRS and LRS.…”

Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

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Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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This paper proposes tiny and error tolerant Convolutional LSTM (ConvLSTM) for event-based vision sensor (EVS) data processing with Computation-in-Memory (CiM) that utilizes ReRAM. To handle the event data by ConvLSTM, the type and parameter of event representation are optimized to pre-process event data. To realize tiny and error tolerant ConvLSTM CiM, reduction of the bit precision and error tolerance in each ConvLSTM layer and weight are considered. On the other hand, reducing the bit precision degrades inference accuracy and error tolerance. ReRAM has non-idealities such as conductance variation and worn out by Set/Reset cycles that induces bit inversion. Thus, bit error rate at each Set/Reset cycles are investigated, and the bit precision of the weight is optimized to accept bit error rate of 0.1% in simulation. The proposed tiny ConvLSTM can reduce the size of memory by 91% compared with non-optimized ConvLSTM of that weight is represented in 32-bit precision.

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Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

“…The 0.1%, 1%, and 10% BERs correspond to 1.0 × 10 4 , 4.0 × 10 4 and 2.4 × 10 5 Set/Reset cycles, respectively. 30,31) As described above, bit precision and bit inversion ratio that is directly expressed as BER are key parameters to estimate the impact on inference accuracy under memory device non-ideality.…”

Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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show abstract

“…ReRAM CiM for IoT edge devices has attracted much attention due to its energy efficiency, high throughput, and scalability. 14,15) ReRAM CiM can solve combinatorial optimization problems by calculating energy using multiply-accumulate (MAC) operations. 15) In this paper, the knapsack problem is discussed, which is one of the combinatorial optimization problems and is also used in financial portfolios.…”

Section: Introductionmentioning

confidence: 99%

“…14,15) ReRAM CiM can solve combinatorial optimization problems by calculating energy using multiply-accumulate (MAC) operations. 15) In this paper, the knapsack problem is discussed, which is one of the combinatorial optimization problems and is also used in financial portfolios. In the case of the knapsack problem, the array area of the conventional ReRAM CiM becomes correspondingly larger because the number of spins for knapsack capacity linearly increases.…”

Section: Introductionmentioning

confidence: 99%

“…3,16) In terms of a ReRAM device, on the one hand, a ReRAM device has reliability issues because ReRAM causes bit-error at high Set/Reset cycles. 15,17,18) On the other hand, as for biterror in SA, it has been reported that searching the optimal answer by controlling the device noise properly is more accurate. 13) Therefore, by co-design of a ReRAM device and log-encoding SA, the influence of the asymmetric ReRAM error characteristics and bit precision on SA is analyzed.…”

Section: Introductionmentioning

confidence: 99%

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97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing

Misawa

Taoka

Matsui

et al. 2022

Jpn. J. Appl. Phys.

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This paper proposes small array area and memory error tolerant resistive random access memory (ReRAM) computation-in-memory (CiM) with hyperparameter optimization based on bit-error rate (BER) and bit precision of log-encoding simulated annealing (SA). For combinatorial optimization problems, the proposed ReRAM CiM with log-encoding SA reduces the array area by 97.6%, compared with the conventional linear-encoding. To analyze ReRAM device error characteristics, “0” and “1” error injection is applied. The asymmetric ReRAM error improves the acceptable BER by 10 times and the acceptable bit precision to 4 bit. By adjusting the random flips and a cooling parameter, the numbers of flips and iterations decrease by 40% and 33%, respectively. Error injected (EI) iteration is changed to reproduce bit-error due to read disturb. The delay of EI iteration increases the acceptable BER by 25%. Furthermore, in the case of requiring extremely high accuracy, hyperparameter optimization improves the probability of obtaining the optimal answer by 1%.

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Ferroelectric compute-in-memory annealer for combinatorial optimization problems

Yin,

Qian,

Vardar

et al. 2024

Nat Commun

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Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications. Various digital annealers, dynamical Ising machines, and quantum/photonic systems have been developed for solving COPs, but they still suffer from the memory access issue, scalability, restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here we report a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer for solving larger-scale COPs efficiently. Our CiM annealer converts COPs into quadratic unconstrained binary optimization (QUBO) formulations, and uniquely accelerates in-situ the core vector-matrix-vector (VMV) multiplication operations of QUBO formulations in a single step. Specifically, the three-terminal FeFET structure allows for lossless compression of the stored QUBO matrix, achieving a remarkably 75% chip size saving when solving Max-Cut problems. A multi-epoch simulated annealing (MESA) algorithm is proposed for efficient annealing, achieving up to 27% better solution and ~ 2X speedup than conventional simulated annealing. Experimental validation is performed using the first integrated FeFET chip on 28nm HKMG CMOS technology, indicating great promise of FeFET CiM array in solving general COPs.

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Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory

Cited by 12 publications

References 2 publications

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing

Ferroelectric compute-in-memory annealer for combinatorial optimization problems

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