Simulated Annealing for VLSI Design

Wong, Daniel Fu Keung; Leong, Hon Wai; Liu, C. L.

doi:10.1007/978-1-4613-1677-0

Cited by 160 publications

(76 citation statements)

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“…Perhaps the best known is the traveling salesman problem, in which one tries to find the minimum trip distance connecting a number of cities. Combinatorial simulated annealing has been used successfully in computer and circuit design [Kirkpatrick et al (1983) and Wong et al (1988)], pollution control [Derwent (1988)], a special case of 0-1 programming [Drexl (1988)], neural networks [Wasserman and Schwartz (1988)], reconstruction of pollycrystalline structures [Telly et al(1987)] and image processing [Carnevali et al (1985)]. …”

Section: B Simulated Annealing For Continuous Variable Problemsmentioning

confidence: 99%

Global optimization of statistical functions with simulated annealing

Goffe

Ferrier

Rogers

1994

Journal of Econometrics

1,412

832

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Section: B Simulated Annealing For Continuous Variable Problemsmentioning

confidence: 99%

Global optimization of statistical functions with simulated annealing

Goffe

Ferrier

Rogers

1994

Journal of Econometrics

1,412

832

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“…Simulated annealing has been applied to solve many VLSI design problems [5]. When applying it to the generation of input pairs, to cause the maximum number of switching gates in a CMOS combinational circuit, we deal with the problems of defining a cost function, and determining a method to generate new inputs pairs to explore the solution space.…”

Section: Application Of Sa To Input Pair Generationmentioning

confidence: 99%

Using simulated annealing to generate input pairs to measure the maximum power dissipation in combinational CMOS circuits

Pawlovsky

2005

IEICE Electron. Express

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Abstract:With the advent of chips that nearly hold 2 billion transistors, low power design is extremely important. We need tools that let us measure the power dissipation of our circuits to choose the lowest power design. For this, we need to generate the inputs that cause the maximum power dissipation in each one of our design choices. In this work we show the results we obtained applying the simulated annealing algorithm in the generation of these input patterns for the ISCAS85 combinational circuits. In our experiments we got for most of the circuits better results than those previously reported elsewhere.

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“…force directed placement [4] or simulated annealing [13], [21]) as well. The running time of the underlying placement algorithm will hardly increase with our framework; the extra work we need is a (very fast) congestion estimation and a few additional repartitioning steps (as described later).…”

Section: Goalsmentioning

confidence: 99%

An effective congestion driven placement framework

Brenner

Rohe

2002

Proceedings of the 2002 International Symposium on Physical Design

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We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

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Simulated Annealing for VLSI Design

Cited by 160 publications

References 0 publications

Global optimization of statistical functions with simulated annealing

Global optimization of statistical functions with simulated annealing

Using simulated annealing to generate input pairs to measure the maximum power dissipation in combinational CMOS circuits

An effective congestion driven placement framework

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