Simulating program disturb faults in flash memories using spice compatible electrical model

Mohammad, M.G.; Saluja, Kewal K.

doi:10.1109/ted.2003.816546

Cited by 19 publications

(15 citation statements)

References 25 publications

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“…The erase and write operations are regulated by the Fowler-Nordheim tunneling effect that modulates the charge quantity in the floating gate and thus the threshold voltage value of the FG-transistor. As in [12], we represent the floating gate by a capacitive charge that varies with the Fowler-Nordheim tunneling effect. Following the law Q0C * U (which is the law defining the electrical charge Q contained in a capacitor C under a potential U), the voltage of this capacitance is proportional to the charges injected or removed.…”

Section: Basics Of the Modelmentioning

confidence: 99%

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Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

et al. 2012

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The embedded Flash (eFlash) technology can be subject to defects creating functional faults. In this paper, we first generalize the electrical model of the ATMEL TSTAC™ eFlash memory technology proposed in [10]. The model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model is validated by means of simulations and comparisons with ATMEL silicon data. Then, we present a complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC™ eFlash array by considering the proposed model on a hypothetical 4×4 array. This analysis highlights the interest of the proposed model to provide a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. Responsible Editor: C. A. Papachristou This paper is an extended version of a previously published paper. Main contributions of this paper with respect to [10] are: -A generalization of the model initially proposed in [10] to the case of multiple word-lines, -A complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC/ eFlash array, -A fault modeling of actual resistive defect injection.

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Section: Basics Of the Modelmentioning

confidence: 99%

“…Up to now, the NOR-based array was preferred to build embedded Flash memories for performance reason, especially the short read access time. Meaningful studies related to electrical simulation models and defect injection for NOR-based array can be found in the literature [3,5,12].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

et al. 2012

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“…For reducing the test complexity, diagonal test and diagnosis algorithms which are performed with diagonally addressing sequence are proposed in [7]. In [4], electrical models for simulating the behavior of disturbance faults are built. In [5], defect-based test algorithms are proposed to optimize the test time of disturbance faults of flash memories.…”

Section: Introductionmentioning

confidence: 99%

Testing Disturbance Faults in Various NAND Flash Memories

Hou

2013

2013 22nd Asian Test Symposium

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NAND flash memory is the most popular nonvolatile memory. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot; some NAND flash memories with single-page wordlines and some with multiple-page wordlines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

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“…Testing of disturbance faults thus is imperative for ensuring the quality of flash memories. Several works of flash memory testing have been proposed in [1,2,[9][10][11]17]. In [9], disturbance faults of flash memories are analyzed and test algorithms for these faults are developed.…”

mentioning

confidence: 99%

“…For reducing the test complexity, diagonal test and diagnosis algorithms which are performed with diagonally addressing sequence are proposed in [3]. In [10], electrical models for simulating the behaviors of disturbance faults are built. In [11], defect-based test algorithms are proposed to optimize the test time of disturbance faults of flash memories.…”

mentioning

confidence: 99%

Testing Disturbance Faults in Various NAND Flash Memories

Hou¹,

Li²

2014

J Electron Test

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NAND flash memory is one popular non-volatile memory. Flash memory is prone to disturbance faults due to its specific mechanism of functional operations. Furthermore, different NAND flash memories might be different on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot; some NAND flash memories with single-page wordlines and some with multiple-page wordlines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are proposed.

show abstract

Simulating program disturb faults in flash memories using spice compatible electrical model

Cited by 19 publications

References 25 publications

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

Testing Disturbance Faults in Various NAND Flash Memories

Testing Disturbance Faults in Various NAND Flash Memories

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