Simulating resistive bridging and stuck-at faults

Abstract

We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.

Process Variation-Aware Test for Resistive Bridges

“…PVAA processes the complete set of PVCs for each bridge location, as shown by the loop between steps 1B and 1G. In step 1C logic faults are identified for bridge b and PVC c using the fault simulation method in [11]. To determine if the identified logic faults are detectable, deterministic test pattern generation is performed in step 1D, using an ATPG-engine based on a solver for the Boolean satisfiability problem [19].…”

“…The defect coverage DC (Eq. 1) of a test T on a parametric bridge b with IC parameters c is expressed in terms of Covered Analogue Detectability Interval (CADI) and Global Analogue Detectability Interval (GADI), representing the covered and 0000-0000/00$00.00 c 2009 IEEE GDSS LTVS BH1 BH2 BH3 BH2 BH4 BH1 BH5 BH6 Th1 0× 0× 0× 0× [10], [11]. We investigated, using SPICE simulations, the behaviour of resistive bridges in the presence of process variation.…”

“…Two experiments were performed. In the first experiment (Table III columns [8][9][10][11][12][13] we kept the original test set of each circuit and augmented it with additional test patterns to reduce test escapes for three weighted average test robustness targets (W A target 0.96, 0.98 and 0.995). Columns marked "WA" show the weighted average robustness of the test sets, evaluated with other PVCs than those that were used in test generation.…”

“…The results show that test sets generated without consideration of process variation are compromised in terms of test quality in the presence of process variation. To regain the lost test quality, additional test patterns can be generated (Table III column [8][9][10][11][12][13]. Alternatively, high test quality in the presence of process variation can be obtained by generating a new test set (Table III column [14][15][16][17][18][19].…”

Diagnosis of Multiple-Voltage Design With Bridge Defect

“…The R sh value corresponding to R 2 is normally referred to as "critical resistance" as it represents the crossing point between faulty and correct logic behavior. Methods for determining the critical resistance have been presented in [21]. A number of bridge resistance intervals can be identified based on the corresponding logic behavior.…”