Simulation analysis of heavy-ion-induced single-event response for nanoscale bulk-Si FinFETs and conventional planar devices

Yu, Junting; Chen, Shuming; Chen, Jianjun; Huang, Pengcheng

doi:10.1007/s11431-016-0241-4

Cited by 2 publications

(2 citation statements)

References 23 publications

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“…We simulated an ion strike at the center of the drain of the struck transistor normally. Similar to our previous works [20][21][22][23][24][25], the included physical models are: (a) Fermi-Dirac statistics, (b) the doping-dependent carrier mobility model with high electric field saturation, carrier-carrier scattering as well as interface scattering; (c) carrier recombination model: doping-dependent SRH and Auger recombination; (d) the effect of bandgap narrowing; (e) hydrodynamic carrier transport model; (f) and other models are configured with default models and parameters.…”

Section: Simulation Detailssupporting

confidence: 81%

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

et al. 2019

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In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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Section: Simulation Detailssupporting

confidence: 81%

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

et al. 2019

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“…We simulated ion strike at the center of drain of the struck transistor normally. Same as our previous works [23][24][25][26][27]…”

Section: Simulation Setupmentioning

confidence: 81%

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Liu

Sun

et al. 2020

Semicond. Sci. Technol.

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In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

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Simulation analysis of heavy-ion-induced single-event response for nanoscale bulk-Si FinFETs and conventional planar devices

Cited by 2 publications

References 23 publications

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

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