Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology

Li, Lixiang; Li, Yuanqing; Wang, Haibin; Li, Rui; Wu, Qiong; Newton, Michael; Ma, Yuan; Chen, Li

doi:10.1007/s10836-015-5549-x

Cited by 5 publications

(4 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In a single irradiation run, we expose DUT to particles for about 1 s, so the dead time is less than 1 %, and thus, it is negligible [16].…”

Section: Test System Setup and Experimental Resultsmentioning

confidence: 99%

“…Li et al proposed a hardened 6 T cell using a variant of circuit layout. Experimental results in 65 nm technology show that its alpha Failure In Time (FIT) rate data is approximately 65 % lower than that of the traditional 6 T cell [16].…”

Section: Introductionmentioning

confidence: 97%

“…This design has been simulated with SPICE models and validated with irradiation results. It has a smaller FIT rate compared to the designs in [14,16]. The rest of the paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

et al. 2016

Self Cite

View full text Add to dashboard Cite

show abstract

“…In a single irradiation run, we expose DUT to particles for about 1 s, so the dead time is less than 1 %, and thus, it is negligible [16].…”

Section: Test System Setup and Experimental Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

See 1 more Smart Citation

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

et al. 2016

Self Cite

View full text Add to dashboard Cite

show abstract

“…Due to scaling of the technology node, the space of the transistor decreases, resulting in a reduced silicon/polysilicon/metal layer area, which makes the device more sensitive to radiation effect. This phenomenon further affects the multiple nodes of the circuit [6][7][8] due to the accumulated charge. Moreover, the SRAM functionality is affected due to the introduction of radiation.…”

Section: Introductionmentioning

confidence: 99%

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

et al. 2023

View full text Add to dashboard Cite

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

show abstract

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets

et al. 2016

J Electron Test

View full text Add to dashboard Cite

Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology

Cited by 5 publications

References 19 publications

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets

Contact Info

Product

Resources

About