Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses

Abstract

Schmitt-Triggers (S/Ts) are often utilized to clean noisy analog signals at intermediate voltage values in digital circuits. However, they are vulnerable to metastability, which may cause the same undesired non-digital output behavior that was supposed to be removed in the first place. To enable an efficient characterization of static and dynamic metastability properties of S/Ts (e.g., the metastable voltages, the resolution time constants and the overall total resolution times), this work introduces multiple simulation approaches based on control theory, AC, DC and transient analyses. The accuracy and runtime of all methods are compared and discussed by applying them to an analytically describable idealized circuit model as well as three common circuit implementations. Altogether, this work represents a comprehensive resource for investigating the metastable behavior in S/Ts. Even more, the proposed methods are applicable beyond the S/T, enabling an efficient characterization of static and dynamic metastable behavior in general circuits as well.

The Hidden Behavior of a D-Latch

“…We want to emphasize that simple DC simulations are sufficient to gather most of the required data. While this is trivially the case for f f and f b , Maier et al [17] have shown that even the (meta)stable values of the S/T, and thus the Latch, can be derived this way. This is based on the key insight that for both stable and metastable states the internal electric currents have to perfectly compensate, since both can be maintained forever.…”

“…This is based on the assumption that the metastable voltage resolves with the time constant τ in an exponential fashion. Maier et al [17], however, recently reported that in real-world S/Ts the trajectories deviate slightly from an ideal exponential, making it impossible to determine a unique τ . Therefore the authors introduced the responsiveness r (V in (t), V out (t)), which allows to model the output voltage for a fixed input voltage as V out (t) = V M ± exp(r (t) • t) with V M denoting the metastable voltage.…”

“…V S S or V D D . The responsiveness is then determined for equidistant output values as they are "passed by" the analog trajectory (for further details refer to [17]). This is a very delicate task, which explains the noisy looking data and occasional outliers.…”

“…In this case the maximum value of V f would be limited to model the output resistance of the assumed V in source. In fact, our chosen Latch model represents an even larger set of circuits, e.g., the (S/T) implementation used in [17], making our results more generally applicable.…”

“…(Meta)stable states of a memory loop (crosses) and an S/T (lines), V in and V out representing the nodes in the loop. Inspired by [17].…”